71M6543F/H and 71M6543G/GH Data Sheet
5
Firmware Interface
5.1
I/O RAM Map –Functional Order
In Table 69 and Table 70, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’.
Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected
to the VBAT pin.
The I/O RAM locations listed in Table 69 have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These
I/O RAM locations are usually modified only at boot-up. The addresses shown in Table 69 are an alternative sequential address to the addresses
from Table 70 which are used throughout this document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM
0x2106[7:5].
Table 69: I/O RAM Map – Functional Order, Basic Configuration
Name
CE6
CE5
CE4
Addr
2000
2001
2002
Bit 7
Bit 6
EQU[2:0]
U
Bit 5
Bit 4
Bit 3
CHOP_E[1:0]
SUM_SAMPS[12:8]
Bit 2
Bit 1
Bit 0
U
RTM_E
CE_E
SUM_SAMPS[7:0]
U
CE3
2003
CE_LCTN[6/5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
CE2
CE1
2004
2005
2006
2007
2008
2009
200A
200B
200C
200D
200E
200F
2010
2011
2012
DIFF6_E
DIFF4_E
U
DIFF2_E
RMT6_E
TMUXR4[2:0]
R
DIFF0_E
RMT4_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
U
CE0
CHOPR[1:0]
RMT2_E
TMUXR6[2:0]
TMUXR2[2:0]
U
RCE0
RTMUX
FOVRD
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
TEMP
LCD0
LCD1
U
U
U
U
U
U
MUX_DIV[3:0]
MUX10_SEL
MUX9_SEL
MUX7_SEL
MUX5_SEL
MUX3_SEL
MUX1_SEL
MUX8_SEL
MUX6_SEL
MUX4_SEL
MUX2_SEL
MUX0_SEL
TEMP_BSEL
LCD_E
TEMP_PWR
OSC_COMP
LCD_MODE[2:0]
TEMP_BAT TBYTE_BUSY
LCD_ALLCOM
TEMP_PER[2:0]
LCD_CLK[1:0]
LCD_Y
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
98
© 2008–2011 Teridian Semiconductor Corporation
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