71M6543F/H and 71M6543G/GH Data Sheet
Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events:
•
•
•
•
Wake-up timer timeout.
Pushbutton (PB) is activated.
A rising edge on SEGDIO4, SEGDIO52 or SEGDIO55.
Activity on the RX or OPT_RX pins.
The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4
Wake-Up Behavior for details.
Table 62 shows the circuit functions available in each operating mode.
Table 62: Available Circuit Functions
System Power
MSN (Mission Mode)
Battery Power
BRN (Brownout Mode)
Circuit Function
LCD SLEEP
PLL_FAST=1 PLL_FAST=0 PLL_FAST=1 PLL_FAST=0
CE (Computation Engine)
FIR
Yes
Yes
--1
--
--
--
--
--
--
Yes
Yes
--
ADC, VREF
PLL
Battery Measurement
Temperature sensor
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
--
Yes
Yes
Yes
--
Yes
Yes
Yes
--
--
--
--
Yes
Boost2
--
Yes
4.92MHz
(from PLL)
Yes
1.57MHz
(from PLL)
Yes
4.92MHz
(from PLL)
Yes
1.57MHz
(from PLL)
Yes
Max MPU clock rate
--
--
MPU_DIV clk. divider
ICE
DIO Pins
Watchdog Timer
LCD
LCD Boost
EEPROM Interface (2-wire)
EEPROM Interface (3-wire)
UART (full speed)
Optical TX modulation
Flash Read
--
--
--
--
--
--
--
--
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
--
Yes
Yes
--
--
--
--
--
--
--
--
38.4kHz
Yes
38.9kHz
Yes
38.4kHz
Yes
38.9kHz
Yes
--
--
Flash Page Erase
Flash Write
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
--
--
--
--
RAM Read and Write
Wakeup Timer
OSC and RTC
DRAM data preservation
NV RAM data preservation
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
--
--
Yes
Yes
--
Yes
Yes
--
Yes
Yes
Yes
Yes
Yes
Yes
Notes:
1. “--“ indicates that the corresponding circuit is not active
2. “Boost” implies that the LCD boost circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6])). The LCD boost
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in
LCD mode, otherwise the PLL is de-activated.
v1.2
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