71M6543F/H and 71M6543G/GH Data Sheet
Priority
Assignment
Interrupt Enable
Individual Flags
Individual
Enable Bits
Logic and Polarity
Selection
Interrupt
Flags
Internal
Source
External
Source
No.
IEN0.0
(EX0)
IEN0.7
(EAL)
DIO status
changed
I T 0
0
DIO
D I O _ R n
T C O N . 1 ( I E 0 )
IP1.0/
IP0.0
IEN2.0
(ES1)
byte received
S 1 C O N . 0 ( R I 1 )
S 1 C O N . 1 ( T I 1 )
UART1
(optical)
> = 1
byte transmitted
IEN0.1
(ET0)
overflow occurred
T C O N . 5 ( T F 0 )
Timer 0
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
IEN1.1
(EX2)
IP1.1/
IP0.1
CE detected zero
crossing
CE detected sag
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
XPULSE
YPULSE
WPULSE
VPULSE
IRCON.1
(IEX2)
I 2 F R
> = 1
IEN0.2
(EX1)
2
Wh pulse
VARh pulse
IEN1.2
(EX3)
IP1.2/
IP0.2
DIO status
changed
DIO
1
3
D I O _ R n
T C O N . 3 ( I E 1 )
IRCON.2
(IEX3)
I 3 F R
CE completed code run and
has new status information
CE_BUSY
IEN0.3
(ET1)
overflow occurred
Timer 1
T C O N . 7 ( T F 1 )
IP1.3/
IP0.3
IEN1.3
(EX4)
IRCON.3
(IEX4)
Supply status changed
byte received
4
VSTAT
IEN0.4
(ES0)
S 0 C O N . 0 ( R I 0 )
UART0
> = 1
> = 1
byte transmitted
IP1.4/
IP0.4
S 0 C O N . 0 ( T I 0 )
IE_EEX
IEN1.4
(EX5)
BUSY fell
IRCON.4
(IEX5)
EX_EEX
EEPROM
SPI
5
6
command
EX_SPI
IE_SPI
received
IP1.5/
IP0.5
IEN1.5
(EX6)
accumulation
EX_XFER
XFER_BUSY
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
cycle completed
IRCON.5
(IEX6)
every second
EX_RTC1S
RTC_1S
RTC_1M
> = 1
every minute
EX_RTC1M
Flag=1
EX0
– EX6 are cleared
means that
an interrupt
has occurred
and has not
been cleared
automaticallywhen the
hardware vectors to the
interrupt handler
Interrupt
Vector
alarm clock
RTC_T
EX_RTCT
3 /1 9 /2 0 1 0
Figure 12: Interrupt Structure
46
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