Electrical Specifications
9.6.6.7
SDRAM DDR2 Interface Test Circuit
Figure 20: SDRAM DDR2 Interface Test Circuit
VDDIO/2
Test Point
50 ohm
CL
9.6.6.8
SDRAM DDR2 Interface AC Timing Diagrams
Figure 21: SDRAM DDR2 Interface Write AC Timing Diagram
tDSH
tDSS
tCH
tCL
CLK
CLKn
DQS
tDQSH
tDQSL
tWPST
tWPRE
DQSn
tDIPW
DQ
tDOVB tDOVA
Figure 22: SDRAM DDR2 Interface Address and Control AC Timing Diagram
tCH
tCL
CLK
CLKn
tIPW
ADDRESS/
CONTROL
tAOVB tAOVA
Copyright © 2008 Marvell
December 6, 2008, Preliminary
MV-S104552-U0 Rev. D
Page 89
Document Classification: Proprietary Information