Electrical Specifications
Table 40: SDRAM DDR2 333 MHz Interface Address and Control Timing Table
333 MHz @ 1.8V
Description
Symbol
tAOIB
Min
-
Max
0.28
0.28
-
Units
ns
Notes
1, 3
Address and Control invalid output time before CLK-CLkn rising edge
Address and Control invalid output time after CLK-CLKn rising edge
Address and Control valid output time before CLK-CLkn rising edge
Address and Control valid output time after CLK-CLKn rising edge
tAOIA
-
ns
1, 3
tAOVB
tAOVA
1.00
1.00
ns
1, 2
-
ns
1, 2
Notes :
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: For all signals, the load is CL = 14 pF.
1. This timing value is defined on CLK / CLKn crossing point.
2. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge.
For more information, see register settings.
3. This timing value is defined w hen Address and Control signals are output on CLK-CLKn rising edge
(1T and 2T configurations). For more information, see register settings.
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 85
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
