Electrical Specifications
9.6.3
Media Independent Interface (MII) AC Timing
9.6.3.1
MII AC Timing Table
Table 33: MII AC Timing Table
Description
Symbol
tSU
Min
8.0
8.0
0.0
Max
Units
ns
Notes
Data input setup relative to RX_CLK rising edge
Data input hold relative to RX_CLK rising edge
Data output delay relative to MII_TX_CLK rising edge
-
-
-
-
tHD
ns
tOV
20.0
ns
1
Notes :
General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.
1. For all signals, the load is CL = 5 pF.
9.6.3.2
MII Test Circuit
Figure 10: MII Test Circuit
Test Point
CL
9.6.3.3
MII AC Timing Diagrams
Figure 11: MII Output Delay AC Timing Diagram
Vih(min)
MII_TX_CLK
Vil(max)
Vih(min)
Vil(max)
TXD, TX_EN, TX_ER
TOV
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 75
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
