88F619x
Hardware Specifications
Figure 5: Power-Up Sequence Example
Voltage
Non-Core Voltage
Core Voltage
70% of
Non-Core
Voltage
70% of Core
Voltage
Reset(s)
Clock(s)
It is the designer's responsibility to verify that the power sequencing requirements
of other components are also met.
Although the non-core voltages can be powered up any time before the core
voltages, allow a reasonable time limitation (for example, 100 ms) between the
first non-core voltage power-up and the last core voltage power-up.
Note
8.1.2
Power-Down Sequence Requirements
There are no special requirements for the core supply to go down before non-core power, or for
reset assertion when powering down (except for VHV, as described below). However, allow a
reasonable time limitation (no more than 100 ms) between the first and last voltage power-down.
When using the eFuse in Burning mode, VHV must be powered down before VDD.
8.2
Hardware Reset
The device has one reset input pin—SYSRSTn. When asserted, the entire chip is placed in its initial
state. Most outputs are placed in high-z, except for the following output pins, that are still active
during SYSRSTn assertion:
M_CLKOUT, M_CLKOUTn
M_CKE
M_ODT
M_STARTBURST
SYSRST_OUTn
Doc. No. MV-S104987-U0 Rev. F
Page 74
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 2, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
