Clocking
7
Clocking
Table 35 lists the clocks in the 88F619x.
Table 35: 88F619x Clocks
Clock Type
Description
•
•
Reference clock:
REF_CLK_XIN (25 MHz)
Derivative clocks:
CPU PLL
- CPU clock
- L2 cache clock
- DDR Clock (the Mbus-L uses the DDR clock.)
NOTE: See Table 38, Reset Configuration, on page 77 for CPU, L2 cache and
DDR frequency configuration.
L2 cache clock frequency must be equal or higher then DDR clock
frequency.
If the SSCG enable bit in the Sampled at Reset register is set, then the
SSCG circuit is applied for the CPU PLL reference clock (refer to the
Sampled at Reset register in the 88F6180, 88F6190, 88F6192, and
88F6281 Functional Specifications).
•
•
Reference clock:
REF_CLK_XIN (25 MHz)
Derivative clocks:
Core PLL
- TCLK (core clock, 166 MHz)
- SDIO Clock (100 MHz)
- Gigabit Ethernet Clock (125 MHz)
- TS unit Clock(100/91/83/77MHz) (88F6192 only)
- SPI clock (TCLK/30–TCLK/4 MHz)
- SMI clock (TCLK/128 MHz)
- TWSI clock (up to TCLK/1600)
NOTE: See Table 38, Reset Configuration, on page 77 for TCLK frequency
configuration.
NOTE: See the TS Interface Configuration register in the 88F6180, 88F6190,
88F6192, and 88F6281 Functional Specifications for TS clock frequency
configuration (88F6192 only).
PEX PHY
There are two options for the reference clock configuration, depending on the PCI
Express clock 100 MHz differential clock:
•
The device uses an external source for PCI Express clock. The PEX_CLK_P
pin is an input.
•
The device uses an internal generated clock for PCI Express clock. The
PEX_CLK_P pin is an output, driving out the PCI Express differential clock.
•
Reference clock:
USB PHY PLL
REF_CLK_XIN (25 MHz)
Copyright © 2008 Marvell
Doc. No. MV-S104987-U0 Rev. F
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Page 71
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
