88F619x
Hardware Specifications
Table 35: 88F619x Clocks (Continued)
Clock Type
Description
•
•
Reference clock:
REF_CLK_XIN (25 MHz)
Derivative clock:
SATA PHY PLL
SATA Clock (150 MHz)
•
Reference clock:
RTC_XIN (32.768 kHz)
RTC
PTP
Used for real time clock functionality, see the Real Time Clock section in the
88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.
•
Reference clock:
PTP_CLK (125 MHz)
The PTP_CLK can be used for the following functions:
•
•
•
PTP time stamp clock
Two options for reference clock:
- PTP_CLK
- Gigabit Ethernet Clock (125 MHz)
TS unit clock
Two options for reference clock:
- PTP_CLK/2
- Core PLL
Audio unit clock
Two options for reference clock:
- PTP_CLK
- REF_CLK_XIN (25 MHz)
For clocking configuration registers, see the 88F6180, 88F6190, 88F6192, and
88F6281 Functional Specifications.
The following table lists the supported combinations of the CPU_CLK Frequency select, CPU_CLK
to DDR CLK ratio, and to CPU_CLK to CPU L2 clock ratio (see Section 8.5, Pins Sample
Configuration, on page 76).
Table 36: Supported Clock Combinations
Device
DDR Clock
(MHz)
CPU to DDR
Clock Ratio
CPU Clock
(MHz)
CPU to L2
Clock Ratio
L2 Clock
(MHz)
88F6190:
88F6192:
200
200
3:1
4:1
600
800
2:1
2:1
300
400
7.1
Spread Spectrum Clock Generator (SSCG)
The SSCG (Spread Spectrum Clock Generator) may be used to generate the spread spectrum clock
for the PLL input. See SSCG Disable in Table 38, Reset Configuration, on page 77, for SSCG
enable/bypass configuration settings.
The SSCG block can be configured to perform up spread, down spread and center spread.
The modulation frequency is configurable. Typical frequency is 30 kHz.
The spread percentage can also be configured up to 1%.
For additional details, see the SSCG Configuration Register description in the 88F6180, 88F6190,
88F6192, and 88F6281 Functional Specifications.
Doc. No. MV-S104987-U0 Rev. F
Page 72
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 2, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
