LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
SIGNAL DEFINITIONS
Power
Outputs
CLKSEL — Clock Select
DO9-0 — Data Output
The CLKSEL control allows the
selection of the active edge of CLK. A
LOW on CLKSEL selects negative-
VCC and GND
The 10-bit data output appears on
DO9-0 on the Nth clock cycle, where N
is the overall delay (desired delay).
edge triggering of the device. Driving
CLKSEL HIGH selects positive-edge
triggering. All timing specifications
are referrenced to the selected active
edge of CLK.
+5 V power supply. All pins must be
connected.
Controls
Clock
LCEN — Length Control Enable
CLK — Master Clock
When LCEN is driven LOW, the next
active clock edge will cause the
loading of the delay value present at
the LC10-0 input.
CLKEN — Clock Enable
The active edge of CLK, selected by
CLKSEL, strobes all registers. All
timing specifications are referenced to
the active edge of CLK.
The Clock Enable control enables and
disables the CLK input. Driving
CLKEN LOW enables CLK and causes
the device to operate in a normal
fashion. When CLKEN is HIGH, CLK
is disabled and the device will hold all
internal operations and data. CLKEN
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
The changing of CLKEN takes effect
on the active edge of CLK following
the edge in which it was latched.
OE — Output Enable
Inputs
The Output Enable controls the state
of DO9-0. Driving OE LOW enables
the output port. When OE is HIGH,
DO9-0 is placed in a high-impedance
state. The internal transfer of data is
not affected by this control.
DI9-0 — Data Input
10-bit data, from the data input, is
latched into the device on the active
edge of CLK when MODSEL is LOW.
LC10-0 — Length Control Input
MODSEL — Mode Select
The 11-bit value is used to specify the
length of the delay buffer, between
DI9-0 and DO9-0, or the amount of
recirculation delay. An integer value
ranging from 0 to 2047 is used to
select a delay ranging from 2 to 2049
clock cycles. The value placed on the
LC10-0 inputs is equal to the desired
delay minus 2. The data presented on
LC10-0 is loaded into the device on the
active edge of CLK, selected by
The Mode Select pin is used to choose
the desired mode of operation: data
delay mode or data recirculation
mode. Driving MODSEL LOW places
the device in the delay mode. The
device operates as a programmable
pipeline register. New data from the
DI9-0 input is loaded on every active
edge of CLK. Driving MODSEL
HIGH places the device in the data
recirculation mode. The device
CLKSEL, in conjunction with LCEN
being driven LOW.
operates as a programmable circular
buffer. The output of the device is
routed back to the input. MODSEL
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
Video Imaging Products
08/16/2000–LDS.9502-G
2
LOGIC [ LOGIC DEVICES INCORPORATED ]
