欢迎访问ic37.com |
会员登录 免费注册
发布采购

LF9502JC25 参数 Datasheet PDF下载

LF9502JC25图片预览
型号: LF9502JC25
PDF下载: 下载PDF文件 查看货源
内容描述: 2K可编程线路缓冲区 [2K Programmable Line Buffer]
分类和应用: 外围集成电路时钟
文件页数/大小: 7 页 / 54 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
 浏览型号LF9502JC25的Datasheet PDF文件第2页浏览型号LF9502JC25的Datasheet PDF文件第3页浏览型号LF9502JC25的Datasheet PDF文件第4页浏览型号LF9502JC25的Datasheet PDF文件第5页浏览型号LF9502JC25的Datasheet PDF文件第6页浏览型号LF9502JC25的Datasheet PDF文件第7页  
LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
DESCRIPTION
The
LF9502
is a high-speed, 10-bit
programmable line buffer. Some
applications the LF9502 is useful for
include sample rate conversion, data
time compression/expansion, soft-
ware controlled data alignment, and
programmable serial data shifting. By
using the MODSEL pin, two different
modes of operation can be selected:
delay mode and data recirculation
mode. The delay mode provides a
minimum of 2 to a maximum of 2049
clock cycles of delay between the
input and output of the device. The
data recirculation mode provides a
feedback path from the data output to
the data input for use as a program-
mable circular buffer.
By using the length control input
(LC
10-0
) and the length control enable
(LCEN) the length of the delay buffer
or amount of recirculation delay can
be programmed. Providing a delay
value on the LC
10-0
inputs and driving
LCEN LOW will load the delay value
into the length control register on the
next selected clock edge. Two regis-
ters, one preceeding the program-
mable delay RAM and one following,
are included in the delay path. There-
fore, the programmed delay value
should equal the desired delay minus
2. This consequently means that the
value loaded into the length control
register must range from 0 to 2047 (to
provide an overall range of 2 to 2049).
The active edge of the clock input,
either positive or negative edge, can
be selected with the clock select
(CLKSEL) input. All timing is based
on the active clock edge selected by
CLKSEL. Data can be held tempo-
rarily by using the clock enable
(CLKEN) input.
FEATURES
u
50 MHz Maximum Operating
Frequency
u
Programmable Buffer Length from
2 to 2049 Clock Cycles
u
10-bit Data Inputs and Outputs
u
Data Delay and Data Recirculation
Modes
u
Supports Positive or Negative Edge
System Clocks
u
Expandable Data Word Width or
Buffer Length
u
44-pin PLCC, J-Lead
LF9502 B
LOCK
D
IAGRAM
MODSEL
LCO
10-0
11
LCEN
REGISTER
REGISTER
11
PROGRAMMABLE
2K DELAY RAM
REGISTER
DI
9-0
10
10
10
REGISTER
10
OE
10
10
MUX
DO
9-0
10
CLKSEL
CLKEN
CLK
CLOCK
GENERATOR
TO ALL REGISTERS
Video Imaging Products
1
08/16/2000–LDS.9502-G