LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
FIGURE 9. SINGLE FILTER, MATRIX MULTIPLY TIMING SEQUENCE
1 Data Set with 16 Coefficient Sets
2
11*
12
13
14
15
17
26***
1
3
16**
CLK
DIN11-0
RIN11-0
DATA SET 0
CF01
DATA SET 0
CAA7-0
CAB7-0
CF00
CF02
CF0A
CF0B
CF0C
CF0D
CF0E
CF0F
CF10
TXFRA/ TXFRB
DOUT15-0
OUT
1
OUT
3
OUT
5
OUT
6
OUT15
OUT
0
OUT
2
OUT4
CENA / CENB
SHENA / SHENB
*
**
***
11 Clocks - First Output of First Data/Coefficient Set
16 Clocks - End of First Data/Coefficient Set
26 Clocks - Final Output of First Data/Coefficient Set
28 clock cycles from the first data
input, DIN15-0; device latency for the
first result is 11 clock cycles
FIGURE 10. DOUBLE WIDE DATA/COEFFICIENT MODE
12
(11+17 = 28). The result will appear at
the corresponding filter output,
I/D
I/D
DIN11-0
REGISTERS
REGISTERS
12
RIN11-0
DOUT15-0. Subsequently, for both dual
and single filter mode configurations,
the sum of products will continue to
appear every clock cycle thereafter
until the matrix dimension has been
realized. The total pipeline latency for
a complete [8x8][8x1]matrix-vector
operation is 26 clock cycles and the
total pipeline latency for a complete
[16x16][16x1]matrix-vector operation
is 43 clock cycles. Therefore, to process
two square matrices simultaneoulsy, of
size N=8, a total of 73 clock cycles are
all that is required. Similarly, to
process a single square matrix, of size
N=16, a total of 283 clock cycles are
required.
FILTER
A
FILTER
B
SCALE
R.S.L.
CIRCUIT
16
DOUT15-0
(Figure 11 and Figure 12 respectively).
Further reference to timing diagram
loading sequence for the RSL registers
are also included in the device data
sheet (Figure 15, Figure 14, and Figure
13). The Filter A and Filter B
LF InterfaceTM are used to load data
into the Filter A and Filter B Configura- access mode, and the data reversal
tion Registers and coefficient banks.
Data/ Coefficient Mode. However,
there are some special considerations
when this mode is desired. The
LF3320 must be configured for single
filter mode only, for a maximum (8x8)
matrix. The user must disable the
cascaded filter mode, the accumulator
Once again, the timing diagrams (see
Figure 8 and 9) will assume that the
Configuration Registers,thecoefficient
sets, and the data values have been
loaded. The corresponding timing
diagram loading sequence for the
coefficient banks and
(see Table 7).
Configuration/ Controlregisters are
included in the LF3320 data sheets
The Matrix Multiplication Mode is
valid in the Double Wide
Double Wide Data/Coefficient Mode
Video Imaging Products
08/16/2000–LDS.3320-N
2-8
LOGIC [ LOGIC DEVICES INCORPORATED ]
