LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
Registers on the rising edge of CLK.
When SHENB is HIGH, data can not be
loaded into the Cascade Registers or
shifted through the I/ D Registers and
their contents will not be changed.
ROUT3-0 are enabled for output. When
OEC is HIGH, COUT11-0 and ROUT3-0
are placed in a high-impedance state.
PAUSEB — LF InterfaceTM Pause
When PAUSEB is HIGH, the Filter B LF
InterfaceTM loading sequence is halted
until PAUSEB is returned to a LOW
state. This effectively allows the user
to load coefficients and control regis-
ters at a slower rate than the master
clock (see the LF InterfaceTM section for
a full discussion).
PAUSEA—LFInterfaceTM Pause
When PAUSEA is HIGH, the Filter A
LF InterfaceTM loading sequence is
halted until PAUSEA is returned to a
LOW state. This effectively allows the
user to load coefficients and control
registers at a slower rate than the
master clock (see the LF InterfaceTM
section for a full discussion).
In Single Filter Mode, SHENB also
enables or disables the loading of data
into the Input (DIN11-0), Reverse
Cascade Output (ROUT11-0) and Filter
A I/ D Registers. It is important to note
that in Single Filter Mode, both
SHENA and SHENB should be
connected together. Both must be
active to enable data loading in Single
Filter Mode. SHENB is latched on the
rising edge ofCLK.
FIGURE 4. SINGLE FILTER MODE
12
12
ROUT11-0
RIN11-0
I/D
I/D
RSLA3-0 — Filter ARound/Select/Limit
Control
12
REGISTERS
DIN11-0
12
REGISTERS
COUT11-0
RSLA3-0 determines which of the
sixteen user-programmable Round/
Select/ Limit registers (RSLregisters)
are used in the Filter A RSL circuitry.
A value of 0 on RSLA3-0 selects RSL
register 0. A value of 1 selects RSL
register 1 and so on. RSLA3-0 is
latched on the rising edge of CLK (see
the round, select, and limit sections for
a complete discussion).
FILTER
A
FILTER
B
RSL
CIRCUIT
16
DOUT15-0
RSLB3-0 — Filter BRound/Select/Limit
Control
RSLB3-0 determines which of the sixteen
user-programmableRSLregistersare
used in the Filter B RSL circuitry. A
value of 0 on RSLB3-0 selects RSL
register 0. A value of 1 selects RSL
register 1 and so on. RSLB3-0 is latched
on the rising edge of CLK (see the round,
select, and limit sections for a complete
discussion).
FIGURE 5. DUAL FILTER MODE
12
RIN11-0
12
I/D
I/D
DIN11-0
REGISTERS
REGISTERS
FILTER
A
FILTER
B
OED —DOUTOutput Enable
When OED is LOW, DOUT15-0 is
enabled for output. When OED is
HIGH, DOUT15-0 is placed in a high-
impedance state.
R.S.L.
R.S.L.
CIRCUIT
CIRCUIT
16
16
OEC—COUT/ROUTOutput Enable
DOUT15-0
ROUT3-0 / COUT11-0
When OEC is LOW, COUT11-0 and
Video Imaging Products
08/16/2000–LDS.3320-N
2-5
LOGIC [ LOGIC DEVICES INCORPORATED ]
