LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
mode,[16x16][16x1]matrix-vector
multiplication.
to be configured for A+B (Table 2 and
Table 4); so that condition A+0 is
ready to begin the matrix-vector
multiplication operation. The current
satisfied. To accomplish this, bit 0 is to data set will not change until
be reset to 0, bit 1 is to be set to 1, and TXFRA/ TXFRBis brought LOW
bit 2 is to be reset to 0. Writing 002H to again. To satisfy the m atrix equ a-
Some functions of the LF3320 must be
disabled when configured for
matrix-vector multiplication. This will
apply to both the single filter mode and
the dual filter mode; these functions
are data reversal and
interleave/ decimation. The LF3320
can be cascaded to realize larger
matrices.
Configuration Register 0(Filter A)and
Configuration Register 2(Filter B)will
set the corresponding registers to
satisfy the A+0 condition.
tion (see Figure 7), the current data set
is held for the duration of the required
matrix dimension while cycling
through each coefficient set
(CENA/ CENBmustbeheld LOW).
During this time new data values can be
load ed serially, read y for the next
activation of TXFRA/ TXFRB. To
insu re the correct evalu ation of the
matrix-vector multiplication
equ ation, it is im p erative that the
coefficient valu es are p aired w ith
their corresp ond ing d ata valu es.
The timing diagrams in Figure 8 and 9
will assume that the Configuration
Registers, the coefficient sets, and the
first set of data values (data set) have
been loaded. Loading input data for an
[8x8][8x1] matrix operation requires 9
clock cycles and loading input data for a
[16x16][16x1] matrix operation requires
17 clock cycles. When configured for an
[8x8][8x1]matrix-vector operation,8
data values are required for loading.
When configured for a [16x16][16x1]
matrix-vector operation, 16 data values
are required for loading. Each data
value is fed through the I/ D Registers,
using the corresponding input.
Data reversal can be disabled by
setting bit 6, ofConfiguration Regis-
ter 1(Filter A)and Configuration
Register 3 (Filter B), both to 1. The
Odd-Tap, interleave mode will need to
be disabled. Writing a 0 to bit 0 of
Configuration Register 1 and Configu-
ration Register 3 will disable the
odd-tap interleave mode for Filter A
and Filter B. When data is not being
interleaved or decimated,the I/ D
Register length should be set to a
length of one (Table 3 and Table 5).
Therefore,writing 040H to Configura-
tion Register 1 and 3 will disable the
data reversal and set the correspond-
ing inherent characteristics for the
desired matrix function.
For the [8x8][8x1]matrix-vector
configuration (dualfilter mode),the
first result will appear 19 clock cycles
from the first data input, DIN15-0
(Filter A)and RIN15-0 (Filter B);device
latency for the first result is 10 clock
cycles (10+9 = 19).
Once the final data value, of the data
set, has been loaded TXFRA/ TXFRB
should be brought LOW for one clock
cycle to complete the loading. Once
this occurs, the data set is then bank
loaded into the respective registers
The result will appear at the corre-
sponding filter output, DOUT15-0
(Filter A) and ROUT3-0/ COUT11-0
(Filter B).For the [16x16][16x1]
matrix-vector configuration (single
filter mode), the first result willappear
The Filter A ALU and Filter B ALU are
FIGURE 8. DUAL FILTER, MATRIX MULTIPLY TIMING SEQUENCE
Data Set 1 with 8 Coefficient Sets
Data Set 2 with 8 Coefficient Sets
2
8*
9
10**
11
18
1
3
17***
CLK
DIN11-0
RIN11-0
DATA SET 0
CF01
DATA SET 1
CF11
CAA7-0
CAB7-0
CF00
CF02
CF07
CF10
CF12
CF17
CF20
CF21
TXFRA/ TXFRB
DOUT15-0
ROUT3-0/COUT15-0
OUT
1
OUT
7
OUT
0
OUT1
OUT
0
CENA / CENB
SHENA / SHENB
*
8 Clocks - End of First Data/Coefficient Set
**
***
10 Clocks - First Output of First Data/Coefficient Set
17 Clocks - Final Output of First Data/Coefficient Set
Video Imaging Products
08/16/2000–LDS.3320-N
2-7
LOGIC [ LOGIC DEVICES INCORPORATED ]
