LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
of loading data into Filter B limit
sets can be updated in less than 27.7 µs, The coefficient banks and
register 7. Data value 3B60H is loaded which is well within vertical blanking
as the lower limit and 72A4H is loaded time. It takes 5S clock cycles to load S
Configuration/ Controlregisters arenot
loaded with data until all data values
for the specified address are loaded into
the LF InterfaceTM. In other words, the
coefficient banks are not written to until
all eight coefficients have been loaded
into theLFInterfaceTM. A round register is
not written to until all four data values
areloaded.
as the upper limit.
round or limit registers. Therefore,it
takes 320 clock cycles to update all
round and limit registers (both Filters A
and B). Assuming an 83 MHz clock
rate, allFilter A and Bround/ limit
registers can be updated in 3.84 µs.
It takes 9S clock cycles to load S
coefficient sets into the device. There-
fore, it takes 2304 clock cycles to load
all 256 coefficient sets. Assuming an
83 MHz clock rate, all 256 coefficient
FIGURE 17. COEFFICIENT BANK LOADING SEQUENCE
COEFFICIENT SET 1
COEFFICIENT SET 2
COEFFICIENT SET 3
CLK
LDA/LDB
W1
W2
W3
CFA/CFB11-0
ADDR
1
COEF
0
COEF
7
ADDR
2
COEF
0
COEF
7
ADDR
3
COEF
0
COEF7
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
FIGURE 18. CONFIGURATION/CONTROL REGISTER LOADING SEQUENCE
CONFIG REG
SELECT REG
ROUND REGISTER
LIMIT REGISTER
CLK
LDA/LDB
W1
W2
W3
W4
CFA/CFB11-0
ADDR
1
DATA
1
ADDR
2
DATA
1
ADDR
3
DATA
1
DATA
2
DATA
3
DATA
4
ADDR
4
DATA
1
DATA
2
DATA
3
DATA4
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
FIGURE 19. COEFFICIENT BANK LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
COEFFICIENT SET 1
CLK
W1
PAUSEA/PAUSEB
LDA/LDB
CFA/CFB11-0
ADDR
1
COEF
0
COEF
1
COEF7
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
Video Imaging Products
08/16/2000–LDS.3320-N
2-16
LOGIC [ LOGIC DEVICES INCORPORATED ]
