LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
OutputAdder
the contents of one of the sixteen Filter
Filter A rounding circuitry. RSLB3-0
determines which ofthe sixteen Filter B
round registers are used in the Filter B
rounding circuitry. A value of 0 on
RSLA/ RSLB3-0 selects Filter A/ B
round register 0. A value of 1 selects
Filter A/ B round register 1 and so
on. RSLA/ RSLB3-0 may be changed
every clock cycle if desired. This
allows the rounding algorithm to be
changed every clock cycle. This is
useful when filtering interleaved
data. If rounding is not desired, a
round register should be loaded with 0
A or Bround registers to the overall
filter,Filter A,or Filter Boutputs(see
Figure 10). TheFilter A round registers
are used for the overall filter (Single
Filter Mode)or Filter A (DualFilter
Mode). TheFilter Bround registersare
used for Filter B(DualFilter Mode).
Each round register is 32-bits wide and
user-programmable. This allows the
filter’s output to be rounded to any
precision required. Since any 32-bit
valuemay beprogrammed into the
round registers, the device can support
The Output Adder adds the Filter A and
B outputs together when the device is in
Single Filter Mode. If 24-bit data and 12-
bit coefficients or 12-bit data and 24-bit
coefficients are desired, the LF3320 can
facilitate this by scaling the Filter B
output by 2-12 before adding it to the
Filter A output. Bit 3 in Configuration
Register 5determines ifthe Filter B
output is scaled before being added to
theFilter Aoutput.
Rounding
complex rounding algorithms as well as and selected as the register used for
standard Half-LSB rounding. RSLA3-0
determines which of the sixteen
Filter A round registers are used in the
rounding. Round register loading is
Theoverallfilter output (SingleFilter
Mode) or Filter A and B outputs (Dual
Filter Mode)may be rounded by adding
discussed in the LF InterfaceTM section.
OutputSelect
The word width of the overall filter,
Filter A, and Filter B outputs is 32-bits.
However, only 16-bits may be sent to
DOUT15-0 (Single or Dual Filter Modes)
and COUT11-0/ ROUT3-0 (Dual Filter
Mode). TheFilter A/ Bselect circuitry
determines which 16-bits are passed
(see Table 1). The Filter A/ B select
registerscontroltheFilter A/ Bselect
circuitry. There are sixteen Filter A
and Bselect registers.
FIGURE 16. FILTER A AND B ROUND/SELECT/LIMIT CIRCUITRY
RSLB3-0
4
DATA IN
32
DATA IN
32
RSLA3-0
4
32
32
RND
RND
The Filter A select registers are used for
theoverallfilter (SingleFilter Mode)or
Filter A (DualFilter Mode). TheFilter B
select registers are used for Filter B(Dual
Filter Mode). Each select register is 5 bits
wide and user-programmable. RSLA3-0
determines which ofthe sixteen Filter A
select registers are used in the Filter A
select circuitry. RSLB3-0 determines
which of the sixteen Filter B select
registers are used in the Filter B select
circuitry. A value of 0 on
32
32
5
5
SELECT
SELECT
16
16
RSLA/ RSLB3-0 selects Filter A/ B select
register 0. A value of 1 selects Filter A/ B
select register 1 and so on.
32
32
LIMIT
LIMIT
RSLA/ RSLB3-0 may be changed every
clock cycle if desired. This allows the
16-bit window to be changed every
clock cycle. This is useful when filtering
interleaved data. Select register load-
ing is discussed in the LF InterfaceTM
section.
FILTER B RSL
FILTER A RSL
16
16
DATA OUT
DATA OUT
Video Imaging Products
08/16/2000–LDS.3320-N
2-13
LOGIC [ LOGIC DEVICES INCORPORATED ]
