LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
register contains an upper and lower
limit value. If the value fed to the
TABLE 4. CONFIGURATION REGISTER 2 – ADDRESS 202H
BITS
FUNCTION
DESCRIPTION
limiting circuitry is less than the lower
limit, the lower limit value is passed as
the filter output. If the value fed to the
limiting circuitry is greater than the
upper limit, the upper limit value is
passed as the filter output. Bit 1 and 0
in Configuration Register 4 enable and
disable Filter A and B limiting respec-
tively. RSLA/ RSLB3-0 may be changed
every clock cycle if desired. This allows
thelimitrangetobechanged everyclock
cycle. This is useful when filtering
interleaved data. When loading limit
values into the device, the upper limit
must be greater than the lower limit.
Limit register loading is discussed in the
LFInterfaceTM section.
0
ALU Mode Filter B
0 : A + B
1 : B – A
1
2
Pass A Filter B
Pass B Filter B
Reserved
0 : ALU Input A = 0
1 : ALU Input A = Forward Register Path
0 : ALU Input B = 0
1 : ALU Input B = Reverse Register Path
11-3
Must be set to “0”
TABLE 5. CONFIGURATION REGISTER 3 – ADDRESS 203H
BITS
FUNCTION
DESCRIPTION
0
Filter B Odd-Tap
Interleave Mode
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
4-1
Filter B I/D Register Length
0000 :
0001 :
0010 :
0011 :
0100 :
0101 :
0110 :
0111 :
1000 :
1001 :
1010 :
1011 :
1100 :
1101 :
1110 :
1111 :
1 Register
2 Registers
3 Registers
4 Registers
5 Registers
6 Registers
7 Registers
8 Registers
9 Registers
1 0 Registers
1 1 Registers
1 2 Registers
1 3 Registers
1 4 Registers
1 5 Registers
1 6 Registers
Coefficient Banks
The coefficient banks store the coeffi-
cients which feed into the multipliers
in Filters A and B. There is a separate
bank for each multiplier. Each bank
can hold 256 12-bit coefficients. The
banks are loaded using an LF
InterfaceTM. There is a separate LF
InterfaceTM for the Filter A and B
banks. Coefficient bank loading is
discussed in the LF InterfaceTM
section.
Configuration and ControlRegisters
5
6
Filter B Tap Number
FilterBDataReversal
Reserved
0 : Even Number of Taps
1 : Odd Number of Taps
Theconfiguration registersdetermine
how the LF3320 operates. Tables 2
through 7 show the formats of the six
configuration registers. There are three
typesofcontrolregisters:round,select,
0 : Data Reversal Enabled
1 : Data Reversal Disabled
11-7
Must be set to “0”
and limit. There are sixteen round
registers for Filter A and sixteen for
Filter B. Each register is 32 bits wide.
RSLA3-0 and RSLB3-0 determine which
Filter A and Bround registersrespec-
tively are used for rounding.
OutputLimiting
registersforboth Filters Aand B. TheFilter
A limitregistersareused for theoverall
filter(SingleFilterMode)orFilter A(Dual
FilterMode). TheFilter Blimitregistersare
used forFilter B(DualFilterMode).
RSLA3-0 determines which of the sixteen
Filter A limitregistersareused in theFilter
A limit circuitry. RSLB3-0 determines
which of the sixteen Filter B limit
registers are used in the Filter B limit
circuitry. A value of 0 on
RSLA/ RSLB3-0 selects Filter A/ B limit
register 0. A valueof1selectsFilter A/ B
limit register 1 and so on. Each limit
An outputlimitingfunction isprovided for
theoverallfilter,Filter A,and Filter B
outputs. TheFilter A limiting circuitry is
used tolimittheoverallfilteroutput(Single
FilterMode)and theFilter Aoutput(Dual
FilterMode). TheFilter Blimitingcircuitry
isused to limit theFilter Boutput (Dual
FilterMode). TheFilter Aand Blimit
registersdeterminethevalid rangeof
outputvaluesfortheFilter Aand B
There are sixteen select registers for
Filter A and sixteen for Filter B. Each
register is 5 bits wide. RSLA3-0 and
RSLB3-0 determine which Filter A and B
select registers respectively are used in
theselect circuitry.
limitingcircuitryrespectively. Thereare
sixteen32-bituser-programmablelimit
Video Imaging Products
08/16/2000–LDS.3320-N
2-14
LOGIC [ LOGIC DEVICES INCORPORATED ]
