L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
NOTES
1. MaximumRatingsindicatestressspecifi- 11. Test conditions assume input transition 20. At any given temperature and voltage
cations only. Functional operation of these times of less than 3 ns, reference levels of condition, output disable time is less than
products at values beyond those indicated 1.5 V, output loading for specified IOL and output enable time for any given device.
in the Operating Conditions table is not IOH plus 30 pF (Fig. 1a), and input pulse
21. Transition is measured ±200 mV from
implied. Exposure to maximum rating con- levels of 0 to 3.0 V (Fig. 2).
steady state voltage with specified loading
ditions for extended periods may affect re-
12. Each parameter is shown as a minimum in Fig. 1b. This parameter is sampled and
liability of the tested device.
or maximum value. Input requirements are not 100% tested.
2. The products described by this specifica- specified from the point of view of the exter-
22. All address timings are referenced from
tion include internal circuitry designed to nal system driving the chip. For example,
the last valid address line to the first transi-
protect the chip from damaging substrate tAVEW is specified as a minimum since the
tioning address line.
injection currents and accumulations of external system must supply at least that
static charge. Nevertheless, conventional much time to meet the worst-case require- 23. CE1, CE2, orWEmustbeinactiveduring
precautions should be observed during ments of all parts. Responses from the inter- address transitions.
storage, handling, and use of these circuits nal circuitry are specified from the point of
24. This product is a very high speed device
in order to avoid exposure to excessive elec- view of the device. Access time, for ex-
and care must be taken during testing in
trical stress values.
ample, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
order to realize valid test information. In-
adequate attention to setups and proce-
dures can cause a good part to be rejected as
faulty. Long high inductance leads that
cause supply bounce must be avoided by
bringing the VCC and ground planes di-
rectly up to the contactor fingers. A 0.01 µF
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at –0.6 V. 13. WE is high for the read cycle.
A current in excess of 100 mA is required to
14. The chip is continuously selected (CE1
reach –2.0 V. The device can withstand in-
low, CE2 high).
definite operation with inputs as low as –3 V
subject only to power dissipation and bond 15. All address lines are valid prior-to or high frequency capacitor is also required
wire fusing constraints.
coincident-with the CE1 and CE2 transition between VCC and ground. To avoid signal
to active.
reflections, proper terminations must be
used.
4. Tested with GND ≤ VOUT ≤ VCC. The de-
vice is disabled, i.e., CE1 = VCC, CE2 = GND. 16. The internal write cycle of the memory
is defined by the overlap of CE1 and CE2
5. A series of normalized curves is available
activeandWElow. Allthreesignalsmustbe
to supply the designer with typical DC and
active to initiate a write. Any signal can
ACparametricinformationforLogicDevices
terminate a write by going inactive. The
Static RAMs. These curves may be used to
address, data, and control input setup and
determine device characteristics at various
hold times should be referenced to the sig-
temperatures and voltage levels.
FIGURE 1a.
R
1 480Ω
+5 V
nalthatbecomesactivelastorbecomesinac-
OUTPUT
6. Tested with all address and data inputs tive first.
changing at the maximum cycle rate. The
17. If WE goes low before or concurrent
device is continuously enabled for writing,
with the latter of CE1 and CE2 going active,
i.e., CE1 ≤ VIL, CE2 ≥ VIH, WE ≤ VIL. Input
the output remains in a high impedance
pulse levels are 0 to 3.0 V.
R
255Ω
2
30 pF
INCLUDING
JIG AND
SCOPE
state.
7. Tested with outputs open and all address
18. If CE1 and CE2 goes inactive before or
and data inputs changing at the maximum
concurrent with WE going high, the output
read cycle rate. The device is continuously
remains in a high impedance state.
FIGURE 1b.
disabled, i.e., CE1 ≥ VIH, CE2 ≤ VIL.
19. Powerup from ICC2 to ICC1 occurs as a
8. Tested with outputs open and all ad-
R
1
480Ω
result of any of the following conditions:
+5 V
dress and data inputs stable. The device
is continuously disabled, i.e., CE1 = VCC, a. Rising edge of CE2 (CE1 active) or the
OUTPUT
CE2 = GND. Input levels are within 0.2 V
of VCC or GND.
falling edge of CE1 (CE2 active).
b. Falling edge of WE (CE1, CE2 active).
R
255Ω
2
INCLUDING
JIG AND
SCOPE
5 pF
9. Data retention operation requires that
VCC never drop below 2.0 V. CE1 must be
≥ VCC – 0.2 V or CE2 must be ≤ 0.2 V. All
c. Transition on any address line (CE1, CE2
active).
other inputs must meet VIN ≥ VCC – 0.2 V or d. Transition on any data line (CE1, CE2,
VIN ≤ 0.2 V to ensure full powerdown. For
low power version (if applicable), this re-
quirement applies only to CE1, CE2, and
and WE active).
The device automatically powers down
FIGURE 2.
from ICC1 to ICC2 after tPD has elapsed from
OBSOLETE
WE; there are no restrictions on data and
address.
any of the prior conditions. This means that
power dissipation is dependent on only
+3.0 V
90%
10%
<3 ns
90%
10. These parameters are guaranteed but cycle rate, and is not on Chip Select pulse
not 100% tested. width.
10%
GND
<3 ns
1M Static RAMs
03/04/99–LDS.108/9-N
5
LOGIC [ LOGIC DEVICES INCORPORATED ]
