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L7C108KM12 参数 Datasheet PDF下载

L7C108KM12图片预览
型号: L7C108KM12
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 128KX8, 12ns, CMOS, CQCC32, CERAMIC, LCC-32]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 9 页 / 166 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
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L7C108/109  
DEVICES INCORPORATED  
128K x 8 Static RAM (Low Power)  
SWITCHING CHARACTERISTICS Over Operating Range  
READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)  
L7C108/109–  
15  
12  
10  
Symbol Parameter  
Min Max Min Max Min Max  
tAVAV  
tAVQV  
tAXQX  
tCLQV  
tCLQZ  
tCHQZ  
tOLQV  
tOLQZ  
tOHQZ  
tPU  
Read Cycle Time  
15  
15  
3
12  
12  
3
10  
10  
3
Address Valid to Output Valid (Notes 13, 14)  
Address Change to Output Change  
15  
15  
12  
12  
10  
10  
Chip Enable Low to Output Valid (Notes 13, 15)  
Chip Enable Low to Output Low Z (Notes 20, 21)  
Chip Enable High to Output High Z (Notes 20, 21)  
Output Enable Low to Output Valid  
4
7
3
6
3
5
Output Enable Low to Output Low Z (Notes 20, 21)  
Output Enable High to Output High Z (Notes 20, 21)  
Input Transition to Power Up (Notes 10, 19)  
Power Up to Power Down (Notes 10, 19)  
Chip Enable High to Data Retention (Note 10)  
0
0
0
0
0
0
0
0
0
4
3
3
tPD  
15  
12  
10  
tCHVL  
READ CYCLE — ADDRESS CONTROLLED Notes 13, 14  
t
AVAV  
ADDRESS  
t
AVQV  
DATA OUT  
PREVIOUS DATA VALID  
AXQX  
DATA VALID  
t
t
PU  
tPD  
I
CC  
READ CYCLE — CE/OE CONTROLLED Notes 13, 15  
t
AVAV  
CE  
t
CLQV  
t
CHQZ  
t
CLQZ  
OE  
t
OLQV  
t
OHQZ  
t
OLQZ  
HIGH IMPEDANCE  
HIGH  
IMPEDANCE  
DATA OUT  
DATA VALID  
t
PU  
tPD  
I
CC  
50%  
50%  
DATA RETENTION Notes 9, 10  
DATA RETENTION MODE  
OBSOLETE  
V
CC  
4.5 V  
4.5 V  
2 V  
t
CHVL  
tAVAV  
CE  
V
IH  
VIH  
1M Static RAMs  
03/04/99–LDS.108/9-N  
3