L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
SWITCHING CHARACTERISTICS Over Operating Range
WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109–
15
12
10
Symbol Parameter
Min Max Min Max Min Max
tAVAV
Write Cycle Time
15
13
0
12
10
0
10
9
tCLEW
tAVBW
tAVEW
tEWAX
tWLEW
tDVEW
tEWDX
tWHQZ
tWLQZ
Chip Enable Low to End of Write Cycle
Address Valid to Beginning of Write Cycle
Address Valid to End of Write Cycle
End of Write Cycle to Address Change
Write Enable Low to End of Write Cycle
Data Valid to End of Write Cycle
0
13
0
10
0
9
0
11
8
9
8
6
5
End of Write Cycle to Data Change
Write Enable High to Output Low Z (Notes 20, 21)
Write Enable Low to Output High Z (Notes 20, 21)
0
0
0
3
3
3
5
5
5
WRITE CYCLE — WE CONTROLLED Notes 16, 17, 18, 19
tAVAV
ADDRESS
CE
tCLEW
tAVEW
tEWAX
tWLEW
WE
tAVBW
tDVEW
tEWDX
DATA IN
DATA OUT
DATA-IN VALID
t
WLQZ
tWHQZ
HIGH IMPEDANCE
PD
tPU
t
tPU
ICC
WRITE CYCLE — CE CONTROLLED Notes 16, 17, 18, 19
tAVAV
ADDRESS
CE
tAVBW
tCLEW
tAVEW
tEWAX
tWLEW
WE
tDVEW
tEWDX
DATA IN
DATA OUT
DATA-IN VALID
OBSOLETE
HIGH IMPEDANCE
tPU
tPD
I
CC
1M Static RAMs
03/04/99–LDS.108/9-N
4
LOGIC [ LOGIC DEVICES INCORPORATED ]
