LTC4270/LTC4271
I2C TIMING DIAGRAMS
SCL
SDA
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0
ACK
AD6
1
0
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
ACK BY
SLAVE
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
42701 F06
Figure 6. Writing to a Register
SCL
SDA
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
AD6
AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
AD6
1
0
1
0
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
REPEATED
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
FRAME 2
DATA BYTE
SERIAL BUS ADDRESS BYTE
42701 F07
Figure 7. Reading from a Register
42701f
12