LTC1771
W U U
U
APPLICATIO S I FOR ATIO
Design Example
0.25W
P -Channel RDS(ON)
=
2
As a design example, assume VIN = 10V (nominal), VIN =
15V(MAX), VOUT = 3.3V, and IMAX = 2A. With this informa-
tion, wecaneasilycalculatealltheimportantcomponents.
3.3V + 0.5V
10V + 0.5V
2A 1.33
( ) (
)
= 0.130Ω
RSENSE = 100mV/2A = 0.05Ω
SincethegateoftheMOSFETwillseethefullinputvoltage,
a MOSFET must be selected whose VGS(MAX) > 15V. A
P-channel MOSFET that meets both the VGS(MAX) and
RDS(ON) requirement is the Si6447DQ.
To optimize low current efficiency, MODE pin is tied to VIN
to enable Burst Mode operation, thus the minimum induc-
tance necessary is:
LMIN = 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH
15µH is chosen for the application.
The most stringent requirement for the Schottky diode
occurs when VOUT = 0V (i.e., short circuit) at maximum
VIN. In this case the worst-case dissipation rises to:
3.3V + 0.5V
∆IL = 3.5µs
= 0.89A
15µH
VIN
V + VD
IN
PD = ISC(AVG)
V
( )
D
For the feedback resistors, choose R1 = 1M to minimize
supply current. R2 can then be calculated to be:
With a 0.05Ω sense resistor ISC(AVG) = 2A will result,
increasing the 0.5V Schottky diode dissipation to 1W.
R2 = (VOUT/1.23 – 1) • R1 = 1.68M
Assume that the MOSFET dissipation is to be limited to
PP = 0.25W.
C
IN is chosen for a RMS current rating of at least 1A at
temperature. COUT is chosen with an ESR of 0.05Ωfor low
output ripple. The output voltage ripple due to ESR is
approximately:
If TA = 70°C and the thermal resistance of the MOSFET is
83°C/W, then the junction temperatures will be 91°C and
δP = 0.33. The required RDS(ON) for the MOSFET can now
be calculated:
V
ORIPPLE ≈ (RESR)(∆IL) = 0.05Ω (0.89AP-P) = 45mVP-P
C
SS
1
2
3
4
8
7
6
5
RUN/SS
MODE
MODE
SENSE
C
ITH
R
ITH
I
TH
LTC1771
R1
V
V
FB
IN
Q1
L
+
+
C
GND
PGATE
D1
IN
R2
C
C
FF
0.1µF
OUT
V
OUT
1771 F03
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 3. LTC1771 Layout Diagram
11
Linear [ Linear ]
