LTC1771
W U U
U
APPLICATIO S I FOR ATIO
Minimum On-Time Considerations
1. Is the Schottky diode closely connected to the drain of
the external MOSFET and the input cap ground?
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC1771 is capable of turning the top MOSFET on
andoffagain.Itisdeterminedbyinternaltimingdelaysand
the amount of gate charge required to turn on the
P-channel MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
2. Is the 0.1µF input decoupling capacitor closely con-
nected between VIN (Pin 6) and ground (Pin 4)? This
capacitor carries the high frequency peak currents.
3. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of COUT and signal
ground. Locate the feedback resistors right next to the
LTC1771. TheVFB lineshouldnotberoutedclosetoany
nodes with high slew rates.
V
OUT + VD
t
ON = tOFF
> tON(MIN)
VIN− VOUT
where tOFF = 3.5µs and tON(MIN) is generally about 0.5µs
4. Is the 1000pF decoupling capacitor for the current
sense resistor connected as close as possible to Pins 6
and 7? Ensure accurate current sensing with Kelvin
connections to the sense resistor.
for the LTC1771.
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC1771 will remain in Burst
Mode operation even at high load currents. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.
5. Is the (+) plate of CIN closely connected to the sense
resistor ? This capacitor provides the AC current to the
MOSFET.
6. Are the signal and power grounds segregated? The
signal ground consists of the (–) plate of COUT, Pin 4 of
theLTC1771andtheresistivedivider.Thepowerground
consists of the Schottky diode anode and the (–) plate
of CIN which should have as short lead lengths as
possible.
Mode Pin
Burst Mode operation is disabled by pulling MODE (Pin 8)
below 0.5V. Disabling Burst Mode operation provides a
lownoiseoutputspectrum, usefulforreducingbothaudio
and RF interference. It does this by keeping the frequency
constant (for fixed VIN) down to much lower load current
(1% to 2% of IMAX) and reducing the amount of output
voltage and current ripple at light loads. When Burst Mode
operation is disabled, efficiency is reduced at light loads
and no load supply current increases to 175µA.
7. Keep the switching node (SW) and the gate node
(PGATE) away from sensitive small signal nodes, espe-
cially the voltage sensing feedback pin (VFB), and mini-
mize their PC trace area.
8. High impedance nodes such as ITH and VFB are very
sensitive to leakage paths on the PC board due to stray
flux, solder, epoxy, etc. Make sure PC board is clean.
Water-soluble solder flux can be especially leaky if not
cleaned properly. Leakage on ITH will manifest itself as
excessive output ripple during Burst Mode operation. If
the problem persists, adding a 10M resistor from Pin 2
to ground should eliminate the problem.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1771. These items are also illustrated graphically in
the layout diagram of Figure 3. Check the following in your
layout:
10
Linear [ Linear ]
