LTM4641
APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
definedJEDECenvironmentconsistentwithJSED51-9and
JESD51-12topredictpowerlossheatflowandtemperature
readings at different interfaces that enable the calculation
of the JEDEC-defined thermal resistance values; (3) the
model and FEA software is used to evaluate the LTM4641
with heat sink and airflow; (4) having solved for and
analyzed these thermal resistance values and simulated
various operating conditions in the software model, a
thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled envi-
ronment chamber while operating the device at the same
power loss as that which was simulated. The outcome of
this process and due diligence yields the set of derating
curves provided in later sections of this data sheet, along
withwell-correlatedJESD51-12-definedθ valuesprovided
in the Pin Configuration section of this data sheet.
for θ
and θ
, respectively. In practice, power
JCtop
JCbottom
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4641, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware
is used to accurately build the mechanical geometry of
the LTM4641 and the specified PCB with all of the cor-
The 6V, 3.3V and 1.5V power loss curves in Figures 18,
19 and 20 respectively can be used in coordination with
the load current derating curves in Figures 21 to 42 for
calculating an approximate θ thermal resistance for the
JA
LTM4641withvariousheatsinkingandairflowconditions.
These thermal resistances represent demonstrated per-
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4641 F17
µMODULE DEVICE
Figure 17. Graphical Representation of JESD51-12 Therꢃal Coefficients
4641f
39
Linear [ Linear ]
