LT3681
APPLICATIONS INFORMATION
6.0
V
OUT
= 3.3V
Synchronization
T
= 25 C
A
5.5
5.0
4.5
4.0
3.5
3.0
L = 4.7
f = 800 kHz
The internal oscillator of the LT3681 can be synchronized
to an external 275kHz to 475kHz clock by using a 5pF
to 20pF capacitor to connect the clock signal to the RT
pin. The resistor tying the RT pin to ground should be
chosen such that the LT3681 oscillates 20% lower than
the intended synchronization frequency (see Setting the
Switching Frequency section).
TO START (RUN/SS = V
)
IN
2.5
2.0
TO START (RUN/SS CONTROL)
TO RUN
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
The LT3681 should not be synchronized until its output
is near regulation as indicated by the PG flag. This can be
done with the system microcontroller/microprocessor or
with a discrete circuit by using the PG output. If a sync
signal is applied while the PG is low, the LT3681 may
exhibit erratic operation.
8.0
7.5
V
A
L = 4.7
= 5.0V
OUT
= 25 C
T
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
f = 800 kHz
When applying a sync signal, positive clock transitions
reset LT3681’s internal clock and negative transitions
initiate a switch cycle. The amplitude of the sync signal
must be at least 2V. The sync signal duty cycle can range
from 5% up to a maximum value given by the following
equation:
TO START (RUN/SS = V
)
IN
3.0
2.5
2.0
TO START (RUN/SS CONTROL)
TO RUN
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3681 F06
Figure 6. The Minimum Input Voltage Depends on
Output Voltage, Load Current and Boost Circuit
⎛
⎞
VOUT + VD
Soft-Start
DCSYNC MAX = 1–
– fSW • 600ns
⎜
⎟
(
)
V – VSW + VD
⎝
⎠
IN
The RUN/SS pin can be used to soft-start the LT3681,
reducing the maximum input current during start-up.
The RUN/SS pin is driven through an external RC filter to
create a voltage ramp at this pin. Figure 7 shows the start-
up and shut-down waveforms with the soft-start circuit.
By choosing a large RC time constant, the peak start-up
current can be reduced to the current that is required to
regulate the output, with no overshoot. Choose the value
oftheresistorsothatitcansupply20µAwhentheRUN/SS
pin reaches 2.3V.
where V
is the programmed output voltage, V is the
D
OUT
diode forward drop, V is the typical input voltage, V
IN
SW
is the switch drop, and f is the desired switching fre-
SW
quency. For example, a 24V input to 5V output at 300kHz
can be synchronized to a square wave with a maximum
duty cycle of 60%. For some applications, such as 12V
IN
to 5V
at 350kHz, the maximum allowable sync duty
OUT
cyclewillbelessthan50%.Ifalowdutycycleclockcannot
be obtained from the system, then a one-shot should be
used between the sync signal and the LT3681. The value
of the coupling capacitor which connects the clock signal
to the RT pin should be chosen based on the clock signal
amplitude. Good starting values for 3.3V and 5V clock
signalsare10pFand5pF,respectively.Thesevaluesshould
be tested and adjusted for each individual application to
assure reliable operation.
I
L
RUN
15k
1A/DIV
RUN/SS
GND
V
RUN/SS
2V/DIV
0.22µF
V
OUT
2V/DIV
3681 F07
2ms/DIV
Figure 7. To Soft-Start the LT3681, Add a Resistor
and Capacitor to the RUN/SS Pin
3681f
15
Linear [ Linear ]
