LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Figure 8 shows the overall loop response with a 330pF VC
capacitor and a typical 100μF tantalum output capacitor.
The response is set by the following terms:
Second, if the loop gain is not rolled sufficiently at the
switching frequency, output ripple will perturb the V pin
C
enough to cause unstable duty cycle switching similar
to subharmonic oscillation. This may not be apparent
at the output. Small signal analysis will not show this
since a continuous time system is assumed. If needed,
an additional capacitor (C ) can be added to the V pin to
Error amplifier:
DC gain set by g and R = 850μ • 500k = 425.
m
L
–1
Pole set by C and R = (2π • 500k • 330p) = 965Hz.
F
L
F
C
–1 –1
Unity-gain set by C and g = (2π • 330p • 850μ )
=
form a pole at typically one fifth the switching frequency
F
m
410kHz.
(If R = ~ 5k, C = ~ 100pF)
C
F
Power stage:
Whencheckingloopstability,thecircuitshouldbeoperated
overtheapplication’sfullvoltage,currentandtemperature
range.Anytransientloadsshouldbeappliedandtheoutput
voltage monitored for a well-damped behavior.
DC gain set by g and R (assume 5Ω) = 5 • 5 = 25.
Pole set by C
Unity-gain set by C
8kHz.
m
L
–1
and R = (2π • 100μ • 10) = 159Hz.
OUT
L
–1 –1
and g = (2π • 100μ • 5 )
=
OUT
m
CONVERTER WITH BACKUP OUTPUT REGULATOR
Tantalum output capacitor:
Zero set by C and C = (2π • 100μ • 0.1) = 15.9kHz.
Insystemswithaprimaryandbackupsupply,forexample,
a battery powered device with a wall adapter input, the
output of the LT1765 can be held up by the backup supply
with its input disconnected. In this condition, the SW pin
–1
OUT
ESR
ThezeroproducedbytheESRofthetantalumoutputcapaci-
tor is very useful in maintaining stability. Ceramic output
capacitors do not have a zero due to very low ESR, but are
dominated by their ESL. They form a notch in the 1MHz to
10MHz range. Without this zero, the V pole must be made
dominant. A typical value of 2.2nF will achieve this.
will source current into the V pin. If the SHDN pin is held
IN
at ground, only the shutdown current of 6μA will be pulled
via the SW pin from the second supply. With the SHDN pin
floating, the LT1765 will consume its quiescent operating
C
current of 1mA. The V pin will also source current to
IN
If better transient response is required, a zero can be
any other components connected to the input line. If this
load is greater than 10mA or the input could be shorted to
ground, a series Schottky diode must be added, as shown
in Figure 9. With these safeguards, the output can be held
added to the loop using a resistor (R ) in series with the
C
compensation capacitor. As the value of R is increased,
C
transient response will generally improve, but two effects
limit its value. First, the combination of output capacitor
at voltages up to the V absolute maximum rating.
IN
ESRandalargeR maystoploopgainrollingoffaltogether.
C
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
80
180
150
120
90
V
C
C
= 5V
OUT
OUT
C
= 100μF, 0.1Ω
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 10 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
60
= 330pF
R /C = 0
C
F
I
= 1A
LOAD
40
PHASE
GAIN
20
configuration with the addition of R3, R4, C and Q1. As
SS
the output starts to rise, Q1 turns on, regulating switch
0
60
current via the V pin to maintain a constant dv/dt at the
C
–20
–40
30
output.Outputrisetimeiscontrolledbythecurrentthrough
C
defined by R4 and Q1’s V . Once the output is in
SS
BE
0
10
100
1k
10k
100k
1M
regulation, Q1 turns off and the circuit operates normally.
FREQUENCY (Hz)
R3 is transient protection for the base of Q1.
1765 F08
Figure 8. Overall Loop Response
1765fd
14
Linear [ Linear ]
