LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
D2
MINIMIZE D1, C3
LT1765 LOOP
CMDSH-3
INPUT
15V
C2
0.18μF
V
IN
C3
GND
4.7μF
CERAMIC
L1
2.7μH
C3
KEEP FB AND V
C
OUTPUT
3.3V
BOOST
COMPONENTS AND
TRACES AWAY FROM
HIGH FREQUENCY,
HIGH INPUT
V
V
C
C
IN
SW
FB
C
D2
2.5A
LT1765-33
C2
OFF ON
SHDN
SYNC GND
COMPONENTS
V
C
C1
4.7μF
CERAMIC
D1
B220A
C
2.2nF
D1
L1
1765 F06
PLACE FEEDTHROUGHS
UNDER AND AROUND
GROUND PAD FOR
GOOD THERMAL
V
OUT
GND
C1
CONDUCTIVITY
KELVIN
SENSE
OUT
1765 F6a
V
Figure 6. Typical Application and Layout (Topside Only Shown)
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and
overall noise.
THERMAL CALCULATIONS
Power dissipation in the LT1765 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit cur-
rent, and input quiescent current. The following formulas
showhowtocalculateeachoftheselosses.Theseformulas
assume continuous mode operation, so they should not
be used for calculating efficiency at light load currents.
The V and FB components should be kept as far away as
C
possible from the switch and boost nodes. The LT1765
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability
or subharmonic like oscillation.
Switch loss:
2
RSW OUT
I
V
OUT
(
) (
)
Board layout also has a significant effect on thermal
resistance. The exposed pad or GND pin is a continuous
copper plate that runs under the LT1765 die. This is the
best thermal path for heat out of the package as can be
P
SW
=
+ 17ns I
V
f
(
OUT)( IN)( )
V
IN
Boost current loss for VBOOST = VOUT:
seen by the low θ of the exposed pad package. Reduc-
2
JC
VOUT
I
V
/50
(
)
OUT
ing the thermal resistance from Pin 4 or exposed pad
onto the board will reduce die temperature and increase
the power capability of the LT1765. This is achieved by
providing as much copper area as possible around this
pin/pad. Also, having multiple solder filled feedthroughs
to a continuous copper plane under LT1765 will help in
reducing thermal resistance. Ground plane is usually suit-
able for this purpose. In multilayer PCB designs, placing a
ground plane next to the layer with the LT1765 will reduce
thermal resistance to a minimum.
PBOOST
=
IN
Quiescent current loss:
PQ =V 0.001
IN
(
)
R
SW
= Switch resistance (≈0.13Ω at hot)
17ns = Equivalent switch current/voltage overlap time
f = Switch frequency
1765fd
12
Linear [ Linear ]
