LTC1402
U
U
U
PIN FUNCTIONS
GAIN (Pin 7): Tie to AGND2 to set the reference voltage to
4.096VortietoVREF tosetthereferencevoltageto2.048V.
(Note 4)
DGND (Pin 13): Digital Ground for Internal Logic. Tie to
solid analog ground plane.
VSS (Pin 14): Negative Supply Voltage. Bypass to solid
analog ground plane with 10µF ceramic (or 10µF tantalum
in parallel with 0.1µF ceramic) or tie directly to the solid
analog ground plane for single supply use. Must be set
more negative than either AIN+ or AIN – . Set to 0V or –5V.
BIP/UNI (Pin 8): Tie to logic low to set the input range to
unipolar mode or tie to logic high to set the input range to
bipolar mode. (Note 4)
OGND (Pin 9): Output Ground for the Output Driver. This
pincanbetiedtothedigitalgroundofthesystem. Allother
ground pins should be tied to the analog ground plane.
SCK (Pin 15): External Clock. Advances the conversion
process and sequences the output data at DOUT on the
risingedge.Respondsto5Vor3VCMOSandtoTTLlevels.
(Note 4). One or more pulses wake from Nap or Sleep.
DOUT (Pin 10): Three-State Data Output. (Note 3) Each
output data word represents the analog input at the start
of the previous conversion.
CONV (Pin 16): Holds the input analog signal and starts
the conversion on the rising edge. Responds to 5V or 3V
CMOS and to TTL levels. (Note 4). Two pulses with SCK in
fixed high or fixed low state start Nap Mode. Four pulses
with SCK in fixed high or fixed low state start Sleep mode.
OVDD (Pin 11):Output Data Driver Power. Tie to VDD when
driving 5V logic. Tie to 3V when driving 3V logic.
DVDD (Pin 12): Digital Power for Internal Logic. Bypass to
DGNDwith10µFceramic(or10µFtantaluminparallelwith
0.1µF ceramic).
W
BLOCK DIAGRA
C
C
SAMPLE
SAMPLE
3
4
+
A
A
IN
IN
1
AV
DD
12
14
DV
DD
–
V
SS
ZEROING SWITCHES
2.048V REF
+
+
REF AMP
COMP
12-BIT CAPACITIVE DAC
–
–
64k
64k
7
5
GAIN
8
BIP/UNI
V
REF
10
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT
DRIVER
6
D
OUT
AGND2
AGND1
DGND
2
11
9
OV
DD
13
INTERNAL
CLOCK
CONTROL LOGIC
OGND
1402 BD
16
15
SCK
CONV
8
Linear [ Linear ]
