LTC1402
POWER REQUIRE E TS
W U
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
4.75
TYP
MAX
5.25
0
UNITS
V
DD
V
SS
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
V
V
–5.25
I
Active Mode
Nap Mode
Sleep Mode
●
●
18
3
2
30
5
10
mA
mA
µA
DD
I
Negative Supply Current
Power Dissipation
Active, Sleep or Nap Modes with SCK Off
●
2
µA
SS
PD
Active Mode with SCK in Fixed State (Hi or Lo)
90
150
mW
W U
TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency (Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Minimum Clock Period
●
●
●
2.2
MHz
SAMPLE(MAX)
455
ns
THROUGHPUT
28
57
10000
ns
SCK
CONV
0
Conversion Time
(Note 9)
14
SCK cycles
14th SCLK↑ to CONV↑ Interval
(Notes 9, 10, 16)
(Note 9)
●
●
●
●
●
●
●
●
●
●
●
●
●
●
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Minimum Positive or Negative SCK Pulse Width
CONV to SCK Setup Time
3.8
7.3
6
1
(Notes 9, 13)
(Note 9)
12
2
SCK After CONV
0
48
4
3
Minimum Positive or Negative CONV Pulse Width
SCKto Sample Mode
(Note 9)
3.5
9
5
14
5
4
(Note 9)
5
CONV to Hold Mode
(Notes 9, 14)
(Note 9)
3.4
6
Minimum Delay Between Conversions
Minimum Delay from SCKto Valid Bits 0 Through 11
Minimum Delay from SCK to Valid REFREADY
7
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 17)
(Notes 9, 17)
9
15
11.4
7
12
20
16
8
8a
9
SCK to Hi-Z at D
OUT
Previous D
Bit Remains Valid After SCK
OUT
10
11
12
REFREADY Bit Delay After Sleep-to-Wake Transition
Settling Time After Sleep-to-Wake Transition
10
2
V
REF
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 6: Linearity, offset and full-scale specifications apply for a single-
+
–
ended A input with A grounded and using the internal reference in
IN IN
bipolar mode with ±5V supplies.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together.
Note 3: When these pins are taken below V or above V , they will be
Note 7: Integral linearity is defined as the deviation of a code from the
straight line passing through the actual endpoints of a transfer curve. The
deviation is measured from the center of quantization band.
SS
DD
clamped by internal diodes. This product can handle input currents greater
than 100mA below V or greater than V without latchup.
Note 8: Bipolar offset is the offset measured from –0.5LSB when the input
SS
DD
flickers between 1000 0000 0000 and 0111 1111 1111.
Note 4: When these pins are taken below V , they will be clamped by
SS
internal diodes. This product can handle input currents greater than
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
100mA below V or greater than V . These pins are not clamped to V .
SS
DD
DD
Note 5: V = 5V, f
specifications and V = –5V for bipolar specifications.
= 2.2MHz, V = 0V for unipolar mode
SS
DD
SAMPLE
Note 11: The analog input range is defined as the voltage difference
+
–
SS
between A and A . The bipolar ±2.048V input range could be used
IN
IN
with a single 5V supply if the absolute voltages of the inputs remain within
the single 5V supply voltage.
4
Linear [ Linear ]
