LTC1400
U U
W U
APPLICATIO S I FOR ATIO
In the Sleep mode, power consumption is reduced to a
minimum by cutting off the supply to all internal circuitry
includingthereference.Figure12showsthewaystopower
down the LTC1400. The chip can enter the Nap mode by
keeping the CLK signal low and pulsing the CONV signal
twice. For Sleep mode operation, CONV signal should be
pulsed four times while CLK is kept low.
Digital Interface
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the D
the conversion result in serial form.
output provides
OUT
Figure13showsthedigitaltimingdiagramoftheLTC1400
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
The LTC1400 can be returned to active mode easily. The
rising edge of CLK will wake-up the LTC1400. During the
to CLK rising edge is less than t , the digital output will
2
transition from Sleep mode to active mode, the V volt-
REF
be delayed by one clock cycle.
age ramp-up time is a function of the loading conditions.
With a 10μF bypass capacitor, the wake-up time from
Sleep mode is typically 4ms. A REFRDY signal will be
activated once the reference has settled and is ready for
The digital output data is updated on the rising edge of the
CLK line. D
data should be captured by the receiving
OUT
system on the rising CLK edge. Data remains valid for a
minimum time of t after the rising CLK edge to allow
capture to occur.
an A/D conversion. This REFRDY bit is output to the D
10
OUT
pin before the rest of the A/D converted code.
t
2
t
7
t
3
1
2
3
4
5
6
7
8
9
10
11
12
13
15
1
2
14
CLK
t
t
5
4
CONV
t
t
6
ACQ
INTERNAL
S/H STATUS
SAMPLE
HOLD
SAMPLE
HOLD
t
8
Hi-Z
Hi-Z
D
OUT
REFRDY D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
REFRDY
t
CONV
t
1400 F13
SAMPLE
Figure 13. ADC Digital Timing Diagram
CLK
CLK
V
V
IH
IH
t
8
t
9
t
10
V
V
90%
10%
OH
OL
D
D
OUT
OUT
1400 F14
Figure 14. CLK to D
Delay
OUT
1400fa
13
Linear [ Linear ]
