LTC1400
U
TYPICAL APPLICATIO S
ADSP2181 Code for Circuit
THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO ADSP-2181
FRAME SYNC PULSE IS GENERATED FROM RFS0
/*Section 3: configure CLKDIV and RFSDIV, setup interrupts*/
/*to configure CLKDIV reg*/
ax0 = 2;
/*Section 1: Initialization*/
dm(0x3FF5) = ax0; /*set the serial clock divide modulus reg
.module/ram/abs = 0 adspltc; /*define the program module*/
SCLKDIV*/
jump start;
/*jump over interrupt vectors*/
/*the input clock frequency = 16.67MHz*/
/*CLKOUT frequency = 2x = 33MHz*/
/*SCLK= 1/2*CLKOUT*1/(SCLKDIV+1)*/
/*for SCLKDIV = 2, SCLK = 33/6 = 5.5MHz*/
/*to Configure RFSDIV*/
nop; nop; nop;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
ax0 = rx0;
/*code vectors here upon IRQ2 int*/
/*code vectors here upon IRQL1 int*/
/*code vectors here upon IRQL0 int*/
/*code vectors here upon SPORT0 TX int*/
/*Section 5*/
ax0 = 15;
/*set the RFSDIV reg = 15*/
/*= > the frame sync pulse for every 16 SCLK*/
/*if frame sync pulse in every 15 SCLK, ax0 = 14*/
dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/
rti;
/* */
/* */
dm(0x3FF4) = ax0;
/*to setup interrupt*/
ifc = 0x0066;
/*end of SPORT0 receive interrupt*/
/*code vectors here upon /IRQE int*/
/*code vectors here upon BDMA interrupt*/
/*code vectors here upon SPORT1 TX (IRQ1) int*/
/*code vectors here upon SPORT1 RX (IRQ0) int*/
/*code vectors here upon TIMER int*/
/*code vectors here upon POWER DOWN int*/
/*clear any extraneous SPORT interrupts*/
/*IRQXB = level sensitivity*/
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
rti; rti; rti; rti;
icntl = 0;
/*disable nesting interrupt*/
/*bit 0 = timer int = 0*/
imask= 0x0020;
/*bit 1 = SPORT1 or IRQ0B int = 0*/
/*bit 2 = SPORT1 or IRQ1B int = 0*/
/*bit 3 = BDMA int = 0*/
/*Section 2: Configure SPORT0*/
start:
/*to configure SPORT0 control reg*/
/*bit 4 = IRQEB int = 0*/
/*bit 5 = SPORT0 receive int = 1*/
/*bit 6 = SPORT0 transmit int = 0*/
/*bit 7 = IRQ2B int = 0*/
/*SPORT0 address = 0X3FF6*/
/*RFS is used for frame sync generation*/
/*RFS0 is internal, TFS is not use*/
/*bit 0-3 = Slen*/
/*F = 15 = 1111*/
/*E = 14 = 1110*/
/*D = 13 = 1101*/
/*bit 4,5 data type right justified zero filled MSB*/
/*bit 6 INVRFS = 0*/
/*enable SPORT0 receive interrupt*/
/*Section 4: Configure System Control Register and Start Communication*/
/*to configure system control reg*/
ax0 = dm(0x3FFF);
ay0 = 0xFFF0;
ar = ax0 AND ay0;
ay0 = 0x1000;
/*read the system control reg*/
/*set wait state to zero*/
ar = ar OR ay0;
dm(0x3FFF) = ar;
/*bit12 = 1, enable SPORT0*/
/*bit 7 INVTFS = 0*/
/*bit 8 IRFS = 1 receive internal frame sync*/
/*bit 9,10,11 are for TFS (don’t care)*/
/*bit 12 TFSW = 1 receive is Normal mode*/
/*bit 13 RTFS = 1 receive is framed mode*/
/*bit 14 ISCLK internal = 1*/
/*frame sync pulse regenerated automatically*/
cntr = 5000;
do waitloop until ce;
nop;
nop;
nop;
nop;
nop;
/*bit 15 multichannel mode = 0*/
/*normal mode, bit12 = 0*/
ax0 = 0x6B0D;
/*if alternate mode bit12 = 1, ax0 = 0x7F0E*/
dm (0x3FF6) =ax0;
nop;
waitloop: nop;
rts;
.endmod;
1400fa
17
Linear [ Linear ]
