LTC3607
applicaTions inForMaTion
5. A ground plane is preferred, but if not available keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. Additionally, the two grounds should not share
3. The resistor divider formed by R1 and R2 must be
connected between the (+) plate of C
and a ground
OUT
sense line terminated near GND (exposed pad). The
feedback signals V and V should be routed away
FB1
FB2
the high current paths of C or C
.
from noisy components and traces (such as the SW
lines) and their traces should be minimized.
IN
OUT
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. These copper areas should be
4. Keep sensitive components away from the SW pins.
ThefeedbackresistorsR1toR4shouldberoutedaway
from the SW traces and the inductors.
connected to V or GND. Refer to Figures 2 and 3 for
IN
board layout examples.
V
8.4V
IN
C
IN2
10µF
C
IN1
10µF
PV
SV
PV
IN2
IN1
IN
MODE/SYNC
RUN1
RUN2
RUN2
100k
L2
3.3µH
RUN1
V
OUT2
2.5V AT 600mA
L1
3.3µH
SW2
LTC3607
V
OUT1
3.3V AT 600mA
SW1
PGOOD2
100k
C2, 22pF
PGOOD1
C1, 22pF
V
FB2
R3, 383k
1%
V
FB1
PGND1 GND SGND PGND2
C
C
R2
121k
1%
OUT2
R1, 549k
1%
OUT1
10µF
R4
121k
1%
10µF
3607 F01
C1: TDK C2012X5R1C106K/1.25
, C : C2012X5R0J106K/1.25
C
OUT1 OUT2
L1, L2: WÜRTH ELEKTRONIK 744025003
Figure 1. Design Example Circuit
V
OUT1
VIAS TO GROUND
PLANE
C
OUT1
VIAS TO GROUND
PLANE
16 15 14 13
1
2
3
4
12
11
10
9
L
VIA TO V
IN
17
C
IN
PIN 1
VIA TO V
GND
IN
5
6
7
8
V
IN
17
GND
VIAS TO
GROUND
PLANE
VIAS TO
GROUND
PLANE
C
IN
C
IN
C
IN
C
OUT1
C
OUT2
L
L
L
VIAS TO GROUND
PLANE
C
OUT2
V
V
V
OUT2
OUT1
IN
V
OUT2
3607 F02
3607 F03
Figure 2. Example of Power Component Layout for
QFN Package
Figure 3. Example of Power Component Layout for
MSE Package
3607fb
14
For more information www.linear.com/LTC3607
Linear Systems [ Linear Systems ]
