LTC3607
applicaTions inForMaTion
Setting the Output Voltage
is selected. This mode provides the lowest output ripple,
at the cost of slightly lower light load efficiency.
The LTC3607 develops a 0.6V reference voltage between
the feedback pins, V
and V , and ground as shown
TheLTC3607canalsobesynchronizedtoanotherLTC3607
by the MODE/SYNC pin. During synchronization, the
mode is set to pulse-skipping and the top switch turn-on
is synchronized to the rising edge of the external clock.
Pulse-skipping mode is also the default mode during
start-up.
FB1
FB2
in Figure 1. The output voltage is set by a resistive divider
according to the following formula:
R1
R2
VOUT =0.6V 1+
Checking Transient Response
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce
the phase margin of the error amp loop.
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
immediately shifts by an amount
To improve the frequency response, a feed-forward ca-
OUT
equal to ΔI
• ESR, where ESR is the effective series
pacitor C may also be used. Great care should be taken
LOAD
FF
resistance of C . ΔI
also begins to charge or dis-
to route the V traces away from noise sources, such as
OUT
LOAD
FB
chargeC
generatingafeedbackerrorsignalusedbythe
the inductor or the SW traces.
OUT
regulator to return V
this recovery time, V
or ringing that would indicate a stability problem.
to its steady-state value. During
can be monitored for overshoot
OUT
OUT
For continuous mode operation with a fixed maximum
input voltage, the minimum value that the output voltage
can be reduced to is set by the minimum on-time, which
is approximately 65ns. For fixed frequency (2.25MHz) ap-
plications, the relation between minimum output voltage
and maximum input voltage is:
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phasemargin.Inaddition,afeed-forwardcapacitorcanbe
added to improve the high frequency response, as shown
in Figure 1. Capacitors C1 and C2 provide phase lead by
creatinghighfrequencyzeroswithR1andR3respectively,
which improve the phase margin.
V
= 0.14625 • V
IN(MAX)
OUT(MIN)
If the output voltage drops below that limit, the output will
still regulate, but the part will skip cycles.
Power Good Outputs
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
The PGOOD1 and PGOOD2 are open-drain outputs which
pull low when a regulator is out of regulation. When the
output voltage is within 8.5% of regulation, a timer is
started which releases the relevant PGOOD pin after 64
clock cycles.
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1μF) input capacitors.
Thedischargedinputcapacitorsareeffectivelyputinparal-
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
Mode Selection & Frequency Synchronization
can deliver enough current to prevent this problem if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
TheMODE/SYNCpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Floating
thispinorconnectingittoa3.3VsourceenablesBurstMode
operation, which provides optimal light load efficiency at
the cost of a slightly higher output voltage ripple. When
this pin is connected to ground, pulse-skipping operation
3607fb
For more information www.linear.com/LTC3607
11
Linear Systems [ Linear Systems ]
