Data Sheet
GE
CAR1212DC series DC-DC converter
Input: -36VD C to -75VDC; Output: 12VDC @ 1200W; 3.3VDC or 5 VDC @ 1A
The signal will be triggered for any state change, including the
following conditions;
Digital Feature Descriptions
PMBus™ compliance: The power supply is fully compliant to the
Power Management Bus (PMBus™) rev1.2 requirements.
•
•
•
•
•
•
•
•
VIN and under or over voltage
IOUT over current
Over Temperature warning or fault
Fan Failure
Communication error
PEC error
Invalid command
Manufacturer specific commands located between addresses 0xD0
to 0xEF provide instructions that either do not exist in the general
PMBus specification or make the communication interface simpler
and more efficient.
Master/Slave: The ‘host controller’ is always the MASTER. Power
supplies are always SLAVES. SLAVES cannot initiate
Internal faults
communications or toggle the Clock. SLAVES also must respond
expeditiously at the command of the MASTER as required by the
clock pulses generated by the MASTER.
The power supply will clear the SMBusAlert# signal (release the
signal to its HI state) upon the following events:
•
•
Receiving a CLEAR_FAULTS command
The main output recycled (turned OFF and then ON) via the
ENABLE signal pin
Clock stretching: The ‘slave’ µController inside the power supply
may initiate clock stretching if it is busy and it desires to delay the
initiation of any further communications. During the clock stretch
the ‘slave’ may keep the clock LO until it is ready to receive further
instructions from the host controller. The maximum clock stretch
interval is 25ms.
•
The main output recycled (turned OFF and then ON) by the
OPERATION command
•
Execution of a READ of the STATUS_WORD register
The host controller needs to recognize this clock stretching, and
refrain from issuing the next clock signal, until the clock line is
released, or it needs to delay the next clock pulse beyond the clock
stretch interval of the power supply.
Global broadcast: This is a powerful command because it can
instruct all power supplies to respond simultaneously in one
command. But it does have a serious disadvantage. Only a single
power supply needs to pull down the ninth acknowledge bit. To be
certain that each power supply responded to the global instruction,
a READ instruction should be executed to each power supply to
verify that the command properly executed. The GLOBAL
BROADCAST command should only be executed for write
instructions to slave devices.
Note that clock stretching can only be performed after completion
of transmission of the 9th ACK bit, the exception being the START
command.
Read back delay: The power supply issues the SMBAlert #
notification as soon as the first state change occurred. During an
event a number of different states can be transitioned to before the
final event occurs. If a read back is implemented rapidly by the host
a successive SMBAlert# could be triggered by the transitioning state
of the power supply. In order to avoid the triggering of successive
SMBAlert# s and thus reading a transitioning state, it is prudent to
wait more than 2 seconds after the receipt of an SMBAlert# before
executing a read back. This delay will ensure that only the final state
of the power supply is captured.
Clock
Stretch
Figure 13. Example waveforms showing clock stretching.
Successive read backs: Successive read backs to the power supply
should not be attempted at intervals faster than every one second.
This time interval is sufficient for the internal processors to update
their data base so that successive reads provide fresh data.
I²C Bus Lock-Up detection: The device will abort any transaction
and drop off the bus if it detects the bus being held low for more
than 35ms.
Communications speed: Both 100kHz and 400kHz clock rates are
supported. The power supplies default to the 100kHz clock rate. The
minimum clock speed specified by SMBus is 10 kHz.
PMBusTM Commands
Packet Error Checking (PEC): Although the power supply will
respond to commands with or without the trailing PEC, it is highly
recommended that PEC be used in all communications. The
integrity of communications is compromised if packet error
correction is not employed. There are many functional features,
including turning OFF the main output, that should require
validation to ensure that the correct command is executed.
Standard instruction: Up to two bytes of data may follow an
instruction depending on the required data content. Analog data is
always transmitted as LSB followed by MSB. PEC is optional and
includes the address and data fields.
1
S
8
1
A
8
1
A
Slave address
Wr
Command Code
PEC is a CRC-8 error-checking byte, based on the polynomial C(x) =
x8 + x2 + x + 1, in compliance with PMBus™ requirements. The
calculation is based in all message bytes, including the originating
write address and command bytes preceding read instructions. The
PEC is appended to the message by the device that supplied the last
byte.
8
1
A
8
1
A
8
PEC
1
A
1
P
Low data byte
High data byte
Master to Slave
Slave to Master
SMBUS annotations; S – Start , Wr – Write, Sr – re-Start, Rd –
Read, A – Acknowledge, NA – not-acknowledged, P – Stop
SMBAlert#: The µC driven SMBAlert# signal informs the
‘master/host’ controller that either a STATE or ALARM change has
occurred. Normally this signal is HI. The signal will change to its LO
level if the power supply has changed states and the signal will be
latched LO until the power supply either receives a ‘clear’ instruction
as outlined below or executes a READ STATUS_WORD. If the alarm
state is still present after the STATUS registers were reset, then the
signal will revert back into its LO state again and will latch until a
subsequent reset signal is received from the host controller.
October 21, 2013
©2013 General Electric Company. All rights reserved.
Page 10
LINEAGEPOWER [ LINEAGE POWER CORPORATION ]
