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AXA003A0X 参数 Datasheet PDF下载

AXA003A0X图片预览
型号: AXA003A0X
PDF下载: 下载PDF文件 查看货源
内容描述: 8.3 - 14VDC输入; 0.75Vdc至5.5VDC输出; 3A输出电流 [8.3 - 14Vdc Input; 0.75Vdc to 5.5Vdc Output; 3A output current]
分类和应用:
文件页数/大小: 18 页 / 573 K
品牌: LINEAGEPOWER [ LINEAGE POWER CORPORATION ]
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Data Sheet  
Austin MiniLynxTM 12V SIP Non-isolated Power Modules:  
March 31, 2008  
8.3 – 14Vdc Input; 0.75Vdc to 5.5Vdc Output; 3A output current  
Test Configurations  
Design Considerations  
Input Filtering  
CURRENT PROBE  
TO OSCILLOSCOPE  
Austin MiniLynxTM 12V SIP module should be  
connected to a low -impedance source. A highly  
LTEST  
VIN(+)  
1μH  
inductive source can affect the stability of the module.  
An input capacitance must be placed directly adjacent  
to the input pin of the module, to minimize input ripple  
voltage and ensure module stability in the presence of  
inductive traces that supply input voltage to the  
module.  
CIN  
CS 1000μF  
Electrolytic  
2x100μF  
Tantalum  
E.S.R.<0.1Ω  
@ 20°C 100kHz  
COM  
In a typical application, a 22 µF low-ESR ceramic  
capacitors will be sufficient to provide adequate ripple  
voltage at the input of the module. To further  
minimize ripple voltage at the input, additional  
ceramic capacitors are recommended at the input of  
the module. Figure 26 shows input ripple voltage  
(mVp-p) for various outputs with a 10 µF or a 22µF  
input ceramic capacitor at full load.  
NOTE: Measure input reflected ripple current with a simulated  
source inductance (LTEST) of 1μH. Capacitor CS offsets  
possible battery impedance. Measure current as shown  
above.  
Figure 23. Input Reflected Ripple Current Test  
Setup.  
COPPER STRIP  
350  
VO(+)  
COM  
RESISTIVE  
LOAD  
1 x 10uF  
300  
1uF  
.
10uF  
SCOPE  
1 x 22uF  
250  
200  
150  
100  
50  
GROUND PLANE  
NOTE: All voltage measurements to be taken at the module  
terminals, as shown above. If sockets are used then  
Kelvin connections are required at the module terminals  
to avoid measurement errors due to socket contact  
resistance.  
Figure 24. Output Ripple and Noise Test Setup.  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
Rdistribution Rcontact  
Rcontact Rdistribution  
Figure 26. Input ripple voltage for various outputs  
with 10 µF or a 22 µF ceramic capacitor at the  
input (full-load).  
VIN(+)  
VO  
RLOAD  
VO  
VIN  
Rdistribution Rcontact  
Rcontact Rdistribution  
COM  
COM  
NOTE: All voltage measurements to be taken at the module  
terminals, as shown above. If sockets are used then  
Kelvin connections are required at the module terminals  
to avoid measurement errors due to socket contact  
resistance.  
Figure 25. Output Voltage and Efficiency Test  
Setup.  
VO. IO  
Efficiency  
=
x
100 %  
η
VIN. IIN  
LINEAGE POWER  
10