MACH211 AND MACH211SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
-6
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input, I/O, or Feedback to Combinatorial
Output
6
7.5
10
12
14
10
15
10
18
12
ns
t
PD
D-type
T-type
5
5.5
0
5.5
6.5
0
6.5
7.5
0
7
8
0
8.5
10
0
10
11
0
12
13.5
0
ns
ns
Setup Time from Input, I/O, or Feedback
to Clock
t
S
Register Data Hold Time
Clock to Output
ns
t
H
4
4.5
6
8
ns
t
CO
LOW
HIGH
2.5
2.5
3
5
5
6
6
6
6
6
7.5
7.5
42
ns
t
WL
Clock Width
3
6
ns
t
WH
D-type 111
T-type 105
D-type 166
T-type 150
200
100
91
80
74
100
91
100
6.5
0
66.7
62.5
83.3
76.9
83.3
7
54
50
69
62.5
83.3
8.5
0
50
MHz
MHz
MHz
MHz
MHz
ns
External
Feedback
1/(t + t
)
S
CO
47.6
66.6
62.5
83.3
10
39
Maximum
Frequency
133
125
167
5.5
0
55.6
51.3
66.7
12
f
MAX
Internal Feedback (f
)
CNT
No Feedback 1/(t + t
)
WL WH
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
5
0
t
SL
0
0
0
ns
t
HL
7
7
13
Gate to Output
7
9
10
14
11
17
11
17
ns
ns
ns
t
(note 6)
13.5
7.5
(note 4)
8
GO
(note 5)
Gate Width LOW
2.5
3
5
6
6
6
7.5
t
GWL
20
(note 6)
20.5
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
9.5
11
12
13
t
PDL
Input Register Setup Time
Input Register Hold Time
1.5
1.5
2
2
2
2
2
2
2
2
2.5
3.5
ns
ns
t
SIR
2.5
2.5
t
HIR
20
(note 6)
22
Input Register Clock to Combinatorial Output
10
15
18
18
ns
t
ICO
D-type
T-type
LOW
8
9
9
10
3
10
11
5
12
13
6
14.5
16
6
15
16
6
18
19.5
7.5
ns
ns
ns
ns
Input Register Clock to Output Register
Setup
t
ICS
2.5
2.5
t
WICL
Input Register
Clock Width
HIGH
3
5
6
6
6
7.5
t
WICH
Maximum Input Register
Frequency
1/(t
+ t
)
200
167
100
83.3
83.3
83.3
66.7
MHz
f
WICL WICH
MAXIR
Input Latch Setup Time
Input Latch Hold Time
1.5
1.5
2
2
2
2
2
2
2
2
2.5
3.5
ns
ns
ns
t
SIL
2.5
2.5
t
HIL
Input Latch Gate to Combinatorial Output
12
13
12
14
14
16
17
19
20
22
20
22
24
t
IGO
Input Latch Gate to Output Through Transparent
Output Latch
26.5
ns
ns
t
IGOL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7
7.5
8.5
9
11
12
14.5
t
SLL
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
9
10
3
11
5
13
6
16
6
16
6
19.5
7.5
ns
ns
t
IGS
2.5
t
WIGL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
12
12.5
14
16
19
19
23
ns
t
PDLL
MACH 1 & 2 Families
27
LATTICE [ LATTICE SEMICONDUCTOR ]
