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MACH211SP-15VC 参数 Datasheet PDF下载

MACH211SP-15VC图片预览
型号: MACH211SP-15VC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能EE CMOS可编程逻辑 [High-Performance EE CMOS Programmable Logic]
分类和应用: 可编程逻辑
文件页数/大小: 48 页 / 1080 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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MACH111 AND MACH111SP  
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1  
-5  
-7  
-10  
-12  
-14  
-15  
-18  
Parameter  
Symbol  
Parameter Description  
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit  
t
Input, I/O, or Feedback to Combinatorial Output  
5
7.5  
10  
12  
14  
10  
15  
10  
18 ns  
PD  
D-type  
T-type  
3.5  
4
5.5  
6.5  
0
6.5  
7.5  
0
7
8
0
8.5  
10  
0
10  
11  
0
12  
13.5  
0
ns  
Setup Time from Input, I/O, or Feedback  
to Clock  
t
S
ns  
ns  
t
Register Data Hold Time  
Clock to Output  
0
H
t
3.5  
5
6
8
12 ns  
ns  
CO  
t
LOW  
HIGH  
2.5  
2.5  
3
5
5
6
6
6
6
7.5  
7.5  
42  
WL  
Clock Width  
t
3
6
6
ns  
WH  
D-type 143  
T-type 133  
D-type 182  
95  
80  
74  
100  
91  
100  
66.7  
62.5  
76.9  
71.4  
83.3  
54  
50  
69  
57  
83.3  
50  
MHz  
External  
Feedback  
1/(t + t )  
S
CO  
87  
47.6  
66.6  
55.5  
83.3  
39  
MHz  
MHz  
MHz  
MHz  
Maximum  
Frequency  
f
133  
125  
167  
53  
MAX  
Internal Feedback (f  
)
CNT  
T-type  
167  
200  
44  
No Feedback 1/(t + t  
)
66.7  
WL WH  
t
Asynchronous Reset to Registered Output  
Asynchronous Reset Width (Note 2)  
7.5  
7.5  
9.5  
9.5  
11  
11  
16  
16  
19.5  
19.5  
20  
20  
24 ns  
AR  
t
4.5  
4.5  
5
5
7.5  
7.5  
12  
8
14.5  
10  
15  
10  
18  
12  
ns  
ns  
ARW  
t
Asynchronous Reset Recovery Time (Note 2)  
Asynchronous Preset to Registered Output  
Asynchronous Preset Width (Note 2)  
ARR  
t
24 ns  
ns  
AP  
t
4.5  
4.5  
5
5
7.5  
7.5  
12  
8
14.5  
10  
15  
10  
18  
12  
APW  
t
Asynchronous Preset Recovery Time (Note 2)  
Input, I/O, or Feedback to Output Enable  
Input, I/O, or Feedback to Output Disable  
ns  
APR  
t
7.5  
7.5  
10  
7
9.5  
9.5  
10  
7
10  
10  
10  
7
12  
12  
10  
7
14.5  
14.5  
10  
7
15  
15  
10  
7
18 ns  
18 ns  
10 ns  
EA  
t
ER  
t
t Increase for Powered-down Macrocell (Note 3)  
PD  
LP  
t
t Increase for Powered-down Macrocell (Note 3)  
7
3
ns  
ns  
LPS  
S
t
t
Increase for Powered-down Macrocell (Note 3)  
Increase for Powered-down Macrocell (Note 3)  
EA  
3
3
3
3
3
3
LPCO  
CO  
t
t
10  
10  
10  
10  
10  
10  
10 ns  
LPEA  
Notes:  
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.  
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where this parameter may be affected.  
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.  
MACH 1 & 2 Families  
25  
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