Specifications ispGDX Family
Applications
The ispGDX family architecture has been developed to Programmable Switch Replacement (PSR)
deliver an in-system programmable signal routing solu-
tion with high speed and high flexibility. The devices are
targeted for three similar but distinct classes of end-
system applications:
Includes solid-state replacement and integration of me-
chanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDX devices can
be driven to HIGH or LOW logic levels to emulate the
traditional device outputs. PSR functions do not require
any input pin connections.
Programmable, Random Signal Interconnect (PRSI)
ThisclassincludesPCB-levelprogrammablesignalrout-
ing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of program-
mable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control in-
puts.
These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDX device will interface
with control logic outputs from other components (such
Programmable Data Path (PDP)
This application area includes system data path trans- as ispLSI) on the board (which frequently change late in
ceiver, MUX and latch functions. With today’s 32- and the design process as control logic is finalized), there
64-bitmicroprocessorbuses,butstandarddatapathglue mustbenorestrictionsonpin-to-pinsignalroutingforthis
components still relegated primarily to eight bits, PCBs type of application.
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of “on-board” bus and memory inter-
PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the pro-
faces that do not require the very high drive of standard
grammableinterconnectisusedtodefinepossible signal
glue functions but can benefit from higher integration.
routes that are then selected dynamically by control
Therefore, there is a need for a flexible means to inte-
signals from an external MPU or control logic. These
gratetheseon-boarddatapathfunctionsinananalogous
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
way to programmable logic’s solution to control logic
integration. Lattice’s ispLSI High-Density PLDs make an
driven by the microprocessor, bus and memory architec-
ideal control logic complement to the ispGDX in-system
ture defined for the system. This part of the design is the
programmable data path devices as shown below.
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate arbitrary any pin-to-any pin re-
routingisnotastrongrequirementaslongasthedesigner
has the ability to define his functions with a reasonable
degree of freedom initially.
Figure 2. ispGDX Complements Lattice ispLSI
Address
Inputs
Control
Inputs
(from µP)
Data Path
Bus #1
(from µP)
ISP/JTAG
Interface
As a result, the ispGDX architecture has been defined to
support PSR and PRSI applications (including bidirec-
tional paths) with no restrictions, while PDP applications
(using dynamic MUXing) are supported with a minimal
number of restrictions as described below. In this way,
speed and cost can be optimized and the devices can still
support the system designer’s needs.
Buffers / Registers
State Machines
Control
Outputs
ispLSI Device
ispGDX Device
Decoders
Buffers / Registers
Configuration
(Switch)
Outputs
The following diagrams illustrate several ispGDX appli-
cations.
System
Clock(s)
Data Path
Bus #2
4
LATTICE [ LATTICE SEMICONDUCTOR ]
