Specifications ispGDX Family
Description (Continued)
ing Pool (GRP). All I/O pin inputs enter the GRP directly In addition, there are no pin-to-pin routing constraints for
or are registered or latched so they can be routed to the 1:1 or 1:n signal routing. That is, any I/O pin configured
required I/O outputs. I/O pin inputs are defined as four as an input can drive one or more I/O pins configured as
sets (A,B,C,D) which have access to the four MUX inputs outputs.
found in each I/O cell. Each output has individual, pro-
grammable I/O tri-state control (OE), output latch clock
(CLK) and two multiplexer control (MUX0 and MUX1)
inputs. Polarity for these signals is programmable for
each I/O cell. The MUX0 and MUX1 inputs control a fast
4:1 MUX, allowing dynamic selection of up to four signal
sources for a given output. OE, CLK and MUX0 and
MUX1 inputs can be driven directly from selected sets of
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
source current and can be tied together in parallel for
greater drive. Programmable output slew rate can be
defined independently for each I/O pin to reduce overall
ground bounce and switching noise.
I/O pins. Optional dedicated clock input pins give mini-
All I/O pins are equipped with IEEE1149.1-compliant
mum clock-to-output delays.
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private com-
mandsorthroughLattice’sindustry-standardISPprotocol.
The BSCAN/ispEN pin is used to make this selection.
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDX devices contain no programmable logic
The ispGDX I/Os are designed to withstand “live inser-
arrays. All input pins include Schmitt trigger buffers for
tion” system environments. The I/O buffers are disabled
noise immunity. These connections are programmed
during power-up and power-down cycles. When design-
ingfor“liveinsertion,”absolutemaximumratingconditions
for the Vcc and I/O pins must still be met. For additional
information, an application note about using Lattice de-
vices in hot swap environments can be downloaded from
the Lattice web site at www.latticesemi.com.
2
into the device using non-volatile E CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
Table 1. ispGDX Family Members
ispGDX DEVICE
ispGDX80A
ispGDX120A
ispGDX160/A
I/O Pins
80
20
120
30
160
40
I/O-OE Inputs*
I/O-Clk Inputs*
20
20
20
2
30
30
30
4
40
40
40
4
I/O-MUXsel1 Inputs*
I/O-MUXsel2 Inputs*
Dedicated Clock Pins
BSCAN / ispEN
TOE
1
1**
4
1
1
4
1
1
4
BSCAN / ISP Interface
RESET
1
1
1
Power/GND
12
25
33
Pin Count/Package
100-Pin TQFP
176-Pin TQFP/
160-Pin PQFP
208-Pin PQFP
272-Ball BGA
* The CLK, OE, MUX0 and MUX1 terminals on each I/O cell can each access 25% of the I/Os.
** MUXed with Y1.
2
LATTICE [ LATTICE SEMICONDUCTOR ]
