Specifications GAL18V10
fmax Descriptions
CLK
CLK
LOGIC
ARRAY
LOGIC
ARRAY
REGISTER
REGISTER
t
su
tco
t
cf
pd
fmax with External Feedback 1/(tsu+tco)
t
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)
CLK
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
LOGIC
REGISTER
ARRAY
t
su + th
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
GND to 3.0V
2ns 10% – 90%
3ns 10% – 90%
1.5V
+5V
-7/-10
-15/-20
R
1
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
3-state levels are measured 0.5V from steady-state active
level.
C L*
Output Load Conditions (see figure)
R
2
Test Condition
R1
R2
CL
A
300Ω
∞
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
B
Active High
Active Low
Active High
Active Low
300Ω
∞
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
C
300Ω
5pF
11
LATTICE [ LATTICE SEMICONDUCTOR ]
