Specifications GAL16LV8ZD
fmax Descriptions
CLK
LOGIC
ARRAY
REGISTER
CLK
LOGIC
ARRAY
t
su
tco
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from
measured tsu and tco.
t
cf
pd
t
CLK
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting
tsu from the period of fmax w/internal feedback (tcf
= 1/fmax - tsu). The value of tcf is used primarily
when calculating the delay from clocking a register
to a combinatorial output (through registered feed-
back), as shown above. For example, the timing
from clock to a combinatorial output is equal to tcf
+ tpd.
LOGIC
REGISTER
ARRAY
t
su + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh
+ twl). This is to allow for a clock duty cycle of other
than 50%.
Switching Test Conditions
+3.3V
Input Pulse Levels
GND to 3.0V
2ns 10% – 90%
1.5V
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
R
1
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level. 3-state to active transitions are measured at (Voh - 0.5)
V and (Vol + 0.5) V.
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Output Load Conditions (see figure)
C L*
R
2
Test Condition
R1
R2
CL
A
270Ω
270Ω
270Ω
270Ω
270Ω
220Ω
220Ω
220Ω
220Ω
220Ω
35pF
35pF
35pF
5pF
B
Active High
Active Low
Active High
Active Low
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
C
5pF
14
LATTICE [ LATTICE SEMICONDUCTOR ]
