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GAL16LV8ZD 参数 Datasheet PDF下载

GAL16LV8ZD图片预览
型号: GAL16LV8ZD
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压,零功率E2CMOS PLD通用阵列逻辑 [Low Voltage, Zero Power E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 18 页 / 269 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16LV8ZD  
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM  
-15  
COM  
-25  
TEST  
DESCRIPTION  
PARAM  
UNITS  
COND.1  
MIN. MAX.  
MIN. MAX.  
tpd  
tco  
tcf2  
tsu  
th  
A
A
Input or I/O to Combinatorial Output  
3
2
15  
10  
8
3
2
25  
15  
10  
ns  
ns  
ns  
ns  
Clock to Output Delay  
Clock to Feedback Delay  
12  
15  
Setup Time, Input or Fdbk before Clk↑  
Hold Time, Input or Fdbk after Clk↑  
A
0
0
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
45.5  
33.3  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
50  
40  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
62.5  
41.6  
twh  
twl  
B
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
Input or I/O to Output Enabled  
OEto Output Enabled  
8
17  
16  
18  
17  
12  
12  
25  
20  
25  
20  
ns  
ns  
ns  
ns  
ns  
ns  
8
ten  
B
tdis  
C
Input or I/O to Output Disabled  
OEto Output Disabled  
C
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Description section.  
3) Refer to fmax Description section.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
TYPICAL  
UNITS  
pF  
TEST CONDITIONS  
VCC = 3.3V, VI = 0V  
VCC = 3.3V, VI/O = 0V  
CI  
8
8
CI/O  
pF  
11  
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