Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA
LFE2M20E/SE
LFE2M35E/SE
Ball
Ball/Pad
Function
Ball/Pad
Function
Dual
Number
Bank
8
8
8
8
8
8
8
8
-
Dual Function
Differential
Bank
8
8
8
8
8
8
8
8
-
Function
WRITEN
CS1N
Differential
M12
M13
PR53B
PR53A
PR52B
PR52A
VCCIO8
PR51B
PR51A
PR50B
GNDIO8
PR50A
PR49B
PR49A
PR48B
VCCIO8
PR48A
PR47B
PR47A
RLM0_PLLCAP
PR45B
GNDIO3
PR45A
PR44B
PR44A
PR43B
VCCIO3
PR43A
PR42B
PR42A
GNDIO3
VCCIO3
PR32B
VCCIO3
PR32A
PR31B
PR31A
GNDIO3
VCCIO3
PR28B
PR28A
PR27B
PR27A
PR25B
PR25A
GNDIO2
PR24B
PR24A
VCCIO2
GNDIO2
PR14B
WRITEN
CS1N
C
T
C
T
PR68B
PR68A
PR67B
PR67A
VCCIO8
PR66B
PR66A
PR65B
GNDIO8
PR65A
PR64B
PR64A
PR63B
VCCIO8
PR63A
PR62B
PR62A
RLM0_PLLCAP
PR60B
GNDIO3
PR60A
PR59B
PR59A
PR58B
VCCIO3
PR58A
PR57B
PR57A
GNDIO3
VCCIO3
PR42B
VCCIO3
PR42A
PR41B
PR41A
GNDIO3
VCCIO3
PR38B
PR38A
PR37B
PR37A
PR35B
PR35A
GNDIO2
PR34B
PR34A
VCCIO2
GNDIO2
PR14B
C
T
C
T
N14
CSN
CSN
N15
D0/SPIFASTN
D0/SPIFASTN
VCCIO
N16
D1
D2
D3
C
T
D1
D2
D3
C
T
M16
L12
C
C
GNDIO
L13
8
8
8
8
8
8
8
8
3
3
-
D4
D5
D6
D7
T
C
T
8
8
8
8
8
8
8
8
3
3
-
D4
D5
D6
D7
T
C
T
L16
K16
L14
C
C
VCCIO
L15
DI/CSSPI0N
DOUT/CSON/CSSPI1N
BUSY/SISPI
T
C
T
DI/CSSPI0N
DOUT/CSON/CSSPI1N
BUSY/SISPI
T
C
T
K13
K14
K11
K15
RLM0_GDLLC_FB_A
C
RLM0_GDLLC_FB_A/RDQ57
C
GNDIO
J16
3
3
3
3
3
3
3
3
-
RLM0_GDLLT_FB_A
RLM0_GDLLC_IN_A
RLM0_GDLLT_IN_A
RLM0_GPLLC_IN_A
T
3
3
3
3
3
3
3
3
-
RLM0_GDLLT_FB_A/RDQ57
RLM0_GDLLC_IN_A**/RDQ57
RLM0_GDLLT_IN_A**/RDQ57
RLM0_GPLLC_IN_A**/RDQ57
T
H16
C (LVDS)*
T (LVDS)*
C
C(LVDS)*
T (LVDS)*
C
J15
J14
VCCIO
J13
RLM0_GPLLT_IN_A
RLM0_GPLLC_FB_A
RLM0_GPLLT_FB_A
T
RLM0_GPLLT_IN_A**/RDQ57
RLM0_GPLLC_FB_A/RDQ57
T
H13
C (LVDS)*
T (LVDS)*
C(LVDS)*
H12
RLM0_GPLLT_FB_A/RDQS57*** T (LVDS)*
GNDIO
VCCIO
G16
3
3
3
3
3
3
-
3
3
3
3
3
3
-
RLM1_SPLLC_FB_A
C
RLM2_SPLLC_FB_A
C
VCCIO
H15
RLM1_SPLLT_FB_A
RLM1_SPLLC_IN_A
RLM1_SPLLT_IN_A
T
RLM2_SPLLT_FB_A
RLM2_SPLLC_IN_A
RLM2_SPLLT_IN_A
T
E16
C (LVDS)*
T (LVDS)*
C(LVDS)*
T (LVDS)*
F15
GNDIO
VCCIO
F16
3
3
3
3
3
2
2
-
3
3
3
3
3
2
2
-
VREF2_3
VREF1_3
C
VREF2_3
VREF1_3
C
G15
T
T
J11
PCLKC3_0
C (LVDS)*
PCLKC3_0
C(LVDS)*
J12
PCLKT3_0
T (LVDS)*
PCLKT3_0
T (LVDS)*
G14
PCLKC2_0/RDQ22
PCLKT2_0/RDQ22
C
T
PCLKC2_0/RDQ32
PCLKT2_0/RDQ32
C
T
G13
GNDIO
F14
2
2
2
-
RDQ22
RDQ22
C (LVDS)*
T (LVDS)*
2
2
2
-
RDQ32
RDQ32
C(LVDS)*
T (LVDS)*
F13
VCCIO
GNDIO
H11
2
C
2
RDQ15
C
4-137
LATTICE [ LATTICE SEMICONDUCTOR ]
