Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA
LFE2M20E/SE
LFE2M35E/SE
Ball
Ball/Pad
Function
Ball/Pad
Function
Dual
Number
Bank
-
Dual Function
Differential
Bank
-
Function
Differential
GNDIO
L2
GNDIO6
PL42B
PL43A
PL43B
VCCIO6
PL44A
PL44B
PL45A
PL45B
GNDIO6
LLM0_PLLCAP
VCCIO6
GNDIO6
TCK
GNDIO6
PL57B
PL58A
PL58B
VCCIO6
PL59A
PL59B
PL60A
PL60B
GNDIO6
LLM0_PLLCAP
VCCIO6
GNDIO6
TCK
6
6
6
6
6
6
6
6
-
LLM0_GPLLC_IN_A
LLM0_GPLLT_FB_A
LLM0_GPLLC_FB_A
C (LVDS)*
6
6
6
6
6
6
6
6
-
LLM0_GPLLC_IN_A**/LDQ57
LLM0_GPLLT_FB_A/LDQ57
LLM0_GPLLC_FB_A/LDQ57
C(LVDS)*
L3
T
T
L4
C
C
VCCIO
M1
LLM0_GDLLT_IN_A
LLM0_GDLLC_IN_A
LLM0_GDLLT_FB_A
LLM0_GDLLC_FB_A
T (LVDS)*
LLM0_GDLLT_IN_A**/LDQ57
LLM0_GDLLC_IN_A**/LDQ57
LLM0_GDLLT_FB_A/LDQ57
LLM0_GDLLC_FB_A/LDQ57
T (LVDS)*
N1
C (LVDS)*
C(LVDS)*
N2
T
T
N3
C
C
GNDIO
M4
6
6
-
6
6
-
VCCIO
GNDIO
K6
-
-
L5
TDI
-
TDI
-
N4
TMS
-
TMS
-
N6
TDO
-
TDO
-
K7
VCCJ
-
VCCJ
-
M5
PB2A
5
5
5
5
5
5
5
5
5
5
-
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
T
C
T
C
T
PB2A
5
5
5
5
5
5
5
5
5
5
-
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
T
C
T
C
T
N5
PB2B
PB2B
L6
PB3A
PB3A
M6
PB3B
PB3B
P3
PB4A
PB4A
VCCIO
P4
VCCIO5
PB4B
VCCIO5
PB4B
BDQ6
BDQ6
BDQ6
BDQS6
C
T
C
T
BDQ6
BDQ6
BDQ6
BDQS6
C
T
C
T
P2
PB5A
PB5A
P1
PB5B
PB5B
R1
PB6A
PB6A
GNDIO
R2
GNDIO5
PB6B
GNDIO5
PB6B
5
5
5
5
5
5
5
-
BDQ6
BDQ6
BDQ6
BDQ6
C
T
C
T
5
5
5
5
5
5
5
-
BDQ6
BDQ6
BDQ6
BDQ6
C
T
C
T
R3
PB7A
PB7A
T2
PB7B
PB7B
R4
PB8A
PB8A
VCCIO
T3
VCCIO5
PB8B
VCCIO5
PB8B
BDQ6
BDQ6
C
T
BDQ6
BDQ6
C
T
T4
PB10A
GNDIO5
PB10B
VCCIO5
GNDIO5
PB16A
PB16B
PB17A
PB17B
VCCIO5
GNDIO5
PB22A
VCCIO4
PB22B
PB10A
GNDIO5
PB10B
VCCIO5
GNDIO5
PB34A
PB34B
PB35A
PB35B
VCCIO5
GNDIO5
PB40A
VCCIO4
PB40B
GNDIO
T5
5
5
-
BDQ6
C
5
5
-
BDQ6
C
VCCIO
GNDIO
T6
5
5
5
5
5
-
VREF2_5/BDQ15
VREF1_5/BDQ15
PCLKT5_0/BDQ15
PCLKC5_0/BDQ15
T
C
T
5
5
5
5
5
-
VREF2_5/BDQ33
VREF1_5/BDQ33
PCLKT5_0/BDQ33
PCLKC5_0/BDQ33
T
C
T
R6
P6
P7
C
C
VCCIO
GNDIO
T7
4
4
4
PCLKT4_0/BDQ24
PCLKC4_0/BDQ24
T
4
4
4
PCLKT4_0/BDQ42
PCLKC4_0/BDQ42
T
VCCIO
T8
C
C
4-135