Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges
TD
Tristate Logic
D
Q
ONEG1
0
1
D-Type
/LATCH
TO
0
1
0
1
D
Q
D
Q
OPOS1
D-Type
Latch
0
1
DDR Output
Registers
Q
D
Q
ONEG0
D
0
1
D-Type
/LATCH
D-Type*
DO
0
1
OPOS0
0
1
0
1
Q
D
Latch
Q
D
Q
D
Q
D
0
1
D-Type*
D-Type
Latch
CLKA
Clock Transfer
Registers
ECLK1
ECLK2
Programmable
0
1
0
1
Control
CLK1
(CLKA)
Output Logic
DQSXFER
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
TD
Tristate Logic
Q
D
ONEG1
0
1
D-Type
/LATCH
TO
0
1
0
1
Q
Q
D
D
OPOS1
D-Type
Latch
Q
Q
D
ONEG0
D
D-Type
/LATCH
DDR Output
Registers
D-Type*
DO
0
1
OPOS0
0
1
D
Q
D
Q
D
Q
D
Q
Latch
D-Type*
Latch
D-Type
CLKB
Clock Transfer
Registers
ECLK1
ECLK2
Programmable
0
0
Control
1
CLK1
1
(CLKB)
DQSXFER
Output Logic
Note: Simplified version does not show CE and SET/RESET details
* Shared with input register
2-34
LATTICE [ LATTICE SEMICONDUCTOR ]
