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ECP2-35 参数 Datasheet PDF下载

ECP2-35图片预览
型号: ECP2-35
PDF下载: 下载PDF文件 查看货源
内容描述: LatticeECP2 / M系列数据表 [LatticeECP2/M Family Data Sheet]
分类和应用:
文件页数/大小: 386 页 / 2475 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Architecture  
LatticeECP2/M Family Data Sheet  
Lattice Semiconductor  
Table 2-12. PIO Signals List  
Name  
Type  
Description  
CE0, CE1  
CLK0, CLK1  
ECLK1, ECLK2  
LSR  
Control from the core  
Control from the core  
Control from the core  
Control from the core  
Control from routing  
Input to the core  
Clock enables for input and output block flip-flops  
System clocks for input and output blocks  
Fast edge clocks  
Local Set/Reset  
GSRN  
INCK2  
Global Set/Reset (active low)  
Input to Primary Clock Network or PLL reference inputs  
DQS signal from logic (routing) to PIO  
Unregistered data input to core  
DQS  
Input to PIO  
INDD  
Input to the core  
INFF  
Input to the core  
Registered input on positive edge of the clock (CLK0)  
Double data rate registered inputs to the core  
Gearbox pipelined inputs to the core  
Gearbox pipelined inputs to the core  
IPOS0, IPOS1  
Input to the core  
QPOS01, QPOS11 Input to the core  
QNEG01, QNEG11 Input to the core  
OPOS0, ONEG0,  
OPOS2, ONEG2  
OPOS1 ONEG1  
DEL[3:0]  
Output data from the core  
Output signals from the core for SDR and DDR operation  
Tristate control from the core  
Control from the core  
Signals to Tristate Register block for DDR operation  
Dynamic input delay control bits  
TD  
Tristate control from the core  
Tristate signal from the core used in SDR operation  
DDRCLKPOL  
DQSXFER  
Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block  
Control from core Controls signal to the Output block  
1. Signals available on left/right/bottom only.  
2. Selected I/O.  
PIO  
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic  
block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selec-  
tion logic.  
Input Register Block  
The input register blocks for PIOs in left, right and bottom edges contain delay elements and registers that can be  
used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous inter-  
faces, before they are passed to the device core. Figure 2-29 shows the diagram of the input register block for left,  
right and bottom edges.The input register block for the top edge contains one memory element to register the input  
signal as shown in Figure 2-30. The following description applies to the input register block for PIOs in the left, right  
and bottom edges of the device.  
Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired, the input signal can  
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and,  
in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed  
delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when  
using a global clock.  
The input block allows three modes of operation. In the single data rate (SDR) the data is registered, by one of the  
registers in the single data rate sync register block, with the system clock. In DDR Mode, two registers are used to  
sample the data on the positive and negative edges of the DQS signal, creating two data streams, D0 and D1.  
These two data streams are synchronized with the system clock before entering the core. Further discussion on  
this topic is in the DDR Memory section of this data sheet.  
2-31  
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