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ECP2-35 参数 Datasheet PDF下载

ECP2-35图片预览
型号: ECP2-35
PDF下载: 下载PDF文件 查看货源
内容描述: LatticeECP2 / M系列数据表 [LatticeECP2/M Family Data Sheet]
分类和应用:
文件页数/大小: 386 页 / 2475 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Pinout Information  
LatticeECP2/M Family Data Sheet  
Lattice Semiconductor  
LatticeECP2M Power Supply and NC  
Signal  
256 fpBGA  
484 fpBGA  
V
G7, G9, H7, J10, K10, K8  
J10, J11, J12, J13, K14, K9, L14, L9, M14, M9, N14,  
N9, P10, P11, P12, P13  
CC  
V
V
V
V
V
V
V
V
V
V
V
V
E7  
B5, B9, E7, H9  
CCIO0  
CCIO1  
CCIO2  
CCIO3  
CCIO4  
CCIO5  
CCIO6  
CCIO7  
CCIO8  
CCJ  
E10  
D13, E16, H14  
E14, G12  
K12, M14  
M10, P12  
M7, P5  
K5, M3  
E3, G5  
T15  
E21, G18, J15, K19  
N19, P15, T18, V21  
AA18, R14, V16, W13  
AA5, R9, V7, W10  
N4, P8, T5, V2  
E2, G5, J8, K4  
AA22, U19  
K7  
W4  
G8, H10, J7, K9  
G10  
H11, H12, L15, L8, M15, M8, R11, R12  
R8, H15, H8, R15  
CCAUX  
CCPLL  
SERDES Power3  
C15, B15, C12, A12, C11, C10, C14, C13, B9, C22, B22, C19, A19, C18, C17, C21, C20, B16, C16,  
C9, C5, C4, C8, C7, A6, C6, B3, C3  
C12, C11, C15, C14, A13, C13, B10, C10  
GND1  
A1, A15, A16, A3, A9, B12, B6, E15, E2, H14,  
H8, H9, J3, J8, J9, M15, M2, P9, R12, R5, T1,  
T16  
A1, A10, A16, A22, AA19, AA4, AB1, AB22, B13,  
B19, B4, D16, D2, D21, D7, G19, G4, H10, H13, J14,  
J9, K10, K11, K12, K13, K15, K20, K3, K8, L10, L11,  
L12, L13, M10, M11, M12, M13, N10, N11, N12, N13,  
N15, N20, N3, N8, P14, P9, R10, R13, T19, T4, W16,  
W2, W21, W7, Y10, Y13  
NC2  
D10, D11, D12, D13, D14, D4, D5, D6, D7, E11, LFE2M20: D14, D15, E14, E15, F13, F14, F15, G12,  
E6, E8, E9, F10, F7, F8, F9  
G13, G14, G15  
LFE2M35: D14, D15, E14, E15, F13, F14, F15, G12,  
G13, G14, G15, U6  
LFE2M50:Y15, W15, AB20, AB21, AA20, AB19,  
AB18, Y22, Y21, Y17, Y18, Y16, W17, Y19, Y20, W19,  
W18, V17, V18, D15, G14, G15, D14, E15, E14, F15,  
F14, F13, G12, G13  
1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual  
number of GND logic connections from the die to the common package GND plane.  
2. NC pins should not be connected to any active signals, VCC or GND.  
3. For package migration across device densities, the designer must comprehend the package pin requirements for the SERDES blocks. Spe-  
cifically, the SERDES power pins of the largest density device must be accounted to accommodate migration to other smaller devices using  
the same package. Please refer to technical note TN1160, LatticeECP2/M Density Migration, for more details.  
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