欢迎访问ic37.com |
会员登录 免费注册
发布采购

ECP2-12 参数 Datasheet PDF下载

ECP2-12图片预览
型号: ECP2-12
PDF下载: 下载PDF文件 查看货源
内容描述: LatticeECP2 / M系列数据表 [LatticeECP2/M Family Data Sheet]
分类和应用:
文件页数/大小: 386 页 / 2475 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号ECP2-12的Datasheet PDF文件第7页浏览型号ECP2-12的Datasheet PDF文件第8页浏览型号ECP2-12的Datasheet PDF文件第9页浏览型号ECP2-12的Datasheet PDF文件第10页浏览型号ECP2-12的Datasheet PDF文件第12页浏览型号ECP2-12的Datasheet PDF文件第13页浏览型号ECP2-12的Datasheet PDF文件第14页浏览型号ECP2-12的Datasheet PDF文件第15页  
Architecture  
LatticeECP2/M Family Data Sheet  
Lattice Semiconductor  
Delay Locked Loops (DLL)  
In addition to PLLs, the LatticeECP2/M family of devices has two DLLs per device.  
CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes  
block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference  
input of the Phase Frequency Detector (PFD) input mux. The reference signal for the PFD can also be generated  
from the Delay Chain and CLKFB signals. The feedback input to the PFD is generated from the CLKFB pin, CLKI  
or from tapped signal from the Delay chain.  
The PFD produces a binary number proportional to the phase and frequency difference between the reference and  
feedback signals. This binary output of the PFD is fed into a Arithmetic Logic Unit (ALU). Based on these inputs,  
the ALU determines the correct digital control codes to send to the delay chain in order to better match the refer-  
ence and feedback signals. This digital code from the ALU is also transmitted via the Digital Control bus (DCNTL)  
bus to its associated DLLDELA delay block. The ALUHOLD input allows the user to suspend the ALU output at its  
current value. The UDDCNTL signal allows the user to latch the current value on the DCNTL bus.  
The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the  
outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output  
to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45,  
22.5 or 11.25 degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with  
optional duty cycle correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK out-  
put signal is asserted when the DLL is locked. Figure 2-6 shows the DLL block diagram and Table 2-5 provides a  
description of the DLL inputs and outputs.  
The user can configure the DLL for many common functions such as time reference delay mode and clock injection  
removal mode. Lattice provides primitives in its design tools for these functions. For more information about the  
DLL, please see the list of additional technical documentation at the end of this data sheet.  
Figure 2-6. Delay Locked Loop Diagram (DLL)  
Delay Chain  
Duty  
Cycle  
50%  
ALUHOLD  
Delay0  
CLKOP  
CLKOS  
Delay1  
Delay2  
Output  
Muxes  
÷4  
÷2  
Duty  
Cycle  
50%  
(from routing  
or external pin)  
Reference  
Phase  
Frequency  
Detector  
Delay3  
Delay4  
CLKI  
Arithmetic  
Logic Unit  
÷4  
÷2  
from CLKOP (DLL  
internal), from clock net  
(CLKOP) or from a user  
clock (pin or logic)  
Feedback  
LOCK  
Lock  
Detect  
CLKFB  
Digital  
DCNTL  
9
Control  
Output  
UDDCNTL  
RSTN  
2-8