Specifications
ispLSI 8600V
Figure 2. ispLSI 8000V GLB Overview
I/O Big Fast Megablock Input Tracks
AND Array Input
Routing
0
General Purpose Big Fast Megablock Input Tracks
Feedback Inputs
20
Product Term
Sharing Array
43
PT 0
PT 1
PT 2
PT 3
Macrocell 0
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To Interconnect
0
From Tristate
Bus Track
PT 4
PT 5
PT 6
PT 7
Macrocell 1
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To Interconnect
1
From Tristate
Bus Track
PT 8
PT 9
PT 10
PT 11
Macrocell 2
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To Interconnect
Fully Populated
AND Array
2
From Tristate
Bus Track
PT 12
PT 13
PT 14
PT 15
Macrocell 3
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To interconnect
3
From Tristate
Bus Track
PT 76
PT 77
PT 78
PT 79
Macrocell 19
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To Interconnect
19
PT 80
From Tristate Bus Track
PT 81
To Output Control MUX
Note: Macrocells 9 and 10 do not support Tristate Bus Feedback.
Function Selector (E
2
Cell Controlled)
5
LATTICE [ LATTICE SEMICONDUCTOR ]
