Specifications
ispLSI 8600V
ispLSI 8000V Family Description (Continued)
version contains 120 Big Fast Megablock I/O and 144
global I/O.
Outputs from the GLBs in a Big Fast Megablock can drive
both the Big Fast Megablock Routing Pool within the Big
Fast Megablock and the Global Routing Plane between
the Big Fast Megablocks. Switching resources are pro-
vided to allow signals in the Global Routing Plane to drive
any or all the Big Fast Megablocks in the device. This
mechanism allows fast, efficient connections, both within
the Big Fast Megablocks and between them.
Each GLB contains 20 macrocells and a fully populated,
programmable AND-array with 82 logic product terms.
The GLB has 44 inputs from the Big Fast Megablock
Routing Pool which are available in both true and comple-
ment form for every product term. Up to 20 of these inputs
can be switched to provide local feedback into the GLB
for logic functions that require it. The 80 general-purpose
product terms can be grouped into 20 sets of four and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 28 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of four product terms or less.
The 20 registered macrocells in the GLB are driven by the
20 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. Each macrocell has two outputs,
one output can be fed back inside the GLB to the AND-
array, while the other output drives both the Big Fast
Megablock Routing Pool and the Global Routing Plane.
This dual output capability from the macrocell allows
efficient use of the hardware resources. One output can
be a registered function for example, while the other
output can be an unrelated combinatorial function.
Macrocell registers can be clocked from one of several
global, local or product term clocks available on the
device. A global, local and product term clock enable is
also provided, eliminating the need to gate the clock to
the macrocell registers. Reset and preset for the macrocell
register is provided from both global and product term
signals. The polarity of all of these control signals is
selectable on an individual macrocell basis. The macro-
cell register can be programmed to operate as a D-type
register, a D-type flow-through latch or a T-type flip flop.
The 20 outputs from the GLB can drive both the Big Fast
Megablock Routing Pool within the Big Fast Megablock
and the Global Routing Plane between the Big Fast
Megablocks. The Big Fast Megablock Routing Pool con-
tains general purpose tracks which interconnect the six
GLBs within the Big Fast Megablock and dedicated
tracks for the signals from the Big Fast Megablock I/O
cells. The Global Routing Plane contains general pur-
pose tracks that interconnect the Big Fast Megablocks
and also carry the signals from the I/Os connected to the
Global Routing Plane.
Control signals for the I/O cell registers are generated
using an extra product term within each GLB, or using
dedicated input pins. Each GLB has two extra product
terms beyond the 80 available for the macrocell logic.
The first additional product term is used as an optional
shared product term clock for all the macrocells within the
GLB. The second additional product term is then routed
to an I/O Control Bus using a separate routing structure
from the Big Fast Megablock Routing Pool and Global
Routing Plane. Use of a separate control bus routing
structure allows the I/O registers to have many control
signals with no impact on the interconnection of the GLBs
and Big Fast Megablocks. The I/O Control Bus is split into
four quadrants, each servicing the I/O cell control re-
quirements for one edge of the device. Signals in the
control bus can be independently selected by any or all
I/O cells to act as clock, clock enable, output enable,
reset or preset.
Each Big Fast Megablock has 24 I/O cells. The Global
Routing Pool has 144 I/O cells. Each I/O cell can be
configured as a combinatorial input, combinatorial out-
put, registered input, registered output or bidirectional
I/O. I/O cell registers can be clocked from one of several
global, local or product term clocks which are selected
from the I/O control bus. A global and product term clock
enable is also provided, eliminating the need for the user
to gate the clock to the I/O cell registers. Reset and preset
for the I/O cell register is provided from both global and
product term signals. The polarity of all of these control
signals is selectable on an individual I/O cell basis. The
I/O cell register can be programmed to operate as a D-
type register or a D-type latch.
The input thresholds are fixed at levels which comply with
both 3.3V and 2.5V interfaces. The output driver can
source 4mA and sink 8mA (3.3V output supply). The
output drivers have a separate VCCIO power supply
which is independent of the main VCC supply for the
device. This feature allows the output drivers to run from
either 3.3V or 2.5V while the device logic is always
3
LATTICE [ LATTICE SEMICONDUCTOR ]
